Method for handling a defective top gate of a source-side injection flash memory array
View Patent ↗A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
1. A method comprising:
determining whether a memory cell has a good top gate and a good wordline;
selecting a redundant memory cell in the event that the memory cell does not have a good top gate and a good wordline;
verifying the memory cell or selected redundant memory cell; and
programming the memory cell or the selected redundant memory cell in the event that the memory cell or the selected redundant memory cell is not verified.
2. The method of claim 1 wherein said programming includes one terminal of said memory cell or bias thereof is fixed or incremental.
3. The method of claim 2 wherein said programming includes other terminals of said memory cell or biases being fixed or incremental.
4. The method of claim 1 wherein said memory cells are source side injection memory cells.
5. The method of claim 1 wherein said memory cells are tip erased memory cells.
6. The method of claim 1 further comprising performing a programming operation that uses a threshold to verify whether said memory cell or said selected redundant memory cell is acceptable for use.
7. The method of claim 6 wherein said programming operation includes cell parameters subject to an increment or count function to determine if the threshold is reached.
8. The method of claim 1 wherein a top gate is operated using capacitance loading and coupling handling.
9. The method of claim 1 wherein gate metal is arranged to minimize a coupling effect between top gate lines.
10. The method of claim 1 wherein top gates are coupled using dynamic coupling or pseudo-dynamic coupling.
11. A method comprising:
determining whether a memory cell has a good top gate;
selecting a redundant memory cell in the event that the memory cell does not have a good top gate;
verifying the memory cell or selected redundant memory cell; and
programming the memory cell or the selected redundant memory cell in the event that the memory cell or the selected redundant memory cell is not verified.
12. The method of claim 11 wherein said programming includes one terminal of said memory cell or bias thereof is fixed or incremental.
13. The method of claim 12 wherein said programming includes other terminals of said memory cell or biases being fixed or incremental.
14. The method of claim 11 wherein said memory cells are source side injection memory cells.
15. The method of claim 11 wherein said memory cells are tip erased memory cells.
16. The method of claim 11 further comprising performing a programming operation that uses a threshold to verify whether said memory cell or said selected redundant memory cell is acceptable for use.
17. The method of claim 16 wherein said programming operation includes cell parameters subject to an increment or count function to determine if the threshold is reached.
18. The method of claim 11 wherein a top gate is provided to enable operation using capacitance loading and coupling handling.
19. The method of claim 11 wherein gate metal is arranged to minimize a coupling effect between top gate lines.
20. The method of claim 11 wherein top gates are provided to enable coupling via dynamic coupling or pseudo-dynamic coupling.