Granted Patent B2

US 9,564,235 · App. 14/386,814 · Granted Feb 7, 2017

Abstract

Claims (29)

1. An apparatus for use in a memory device, comprising:

a trim controller;

a trimmable current reference generator for outputting a reference current;

one or more selected memory cells; and

a comparator for comparing the reference current with the current drawn by the one or more selected memory cells to generate an output indicative of a value stored in the selected memory cell,

wherein the trim controller monitors output of the comparator, controls the resistance of a variable resistor, and determines the optimum level of resistance of the variable resistor.

2. The apparatus of claim 1 , wherein the selected memory cell is a split gate non-volatile memory cell.

3. The apparatus of claim 2 , wherein the selected memory cell can store one of two different values.

4. The apparatus of claim 2 , wherein the selected memory cell can store one of four different values.

5. The apparatus of claim 1 , wherein the trimmable current reference generator comprises a variable resistor.

6. The apparatus of claim 2 , wherein the trimmable current reference generator comprises a variable resistor.

7. The apparatus of claim 3 , wherein the trimmable current reference generator comprises a variable resistor.

8. The apparatus of claim 4 , wherein the trimmable current reference generator comprises a variable resistor.

9. The apparatus of claim 1 , further comprising a current mirror.

10. A method of generating a reference to read one or more selected memory cells, comprising:

generating current using a trimmable current reference generator;

drawing current using one or more selected memory cells;

comparing the current generated by the trimmable current reference generator with the current drawn by the one or more selected memory cells; and

determining the optimum level of resistance of a variable resistor by increasing the amount of resistance in the variable resistor until a comparator output changes.

11. The method of claim 10 , wherein the selected memory cell is a split gate non-volatile memory cell.

12. The method of claim 11 , wherein the selected memory cell can store one of two different values.

13. The method of claim 11 , wherein the selected memory cell can store one of four different values.

14. The method of claim 10 , wherein the trimmable current reference generator comprises a variable resistor.

15. The method of claim 11 , wherein the trimmable current reference generator comprises a variable resistor.

16. The method of claim 12 , wherein the trimmable current reference generator comprises a variable resistor.

17. The method of claim 13 , wherein the trimmable current reference generator comprises a variable resistor.

18. The method of claims 10 , wherein the method of generating a reference to read one or more selected memory cells further comprises determining the average of the various resistance levels identified that caused comparator output to change.

19. The method of claim 18 , wherein the method of generating a reference to read one or more selected memory cells further comprises storing the average value to be used during read operations.

20. The method of claim 10 , wherein the method of generating a reference to read one or more selected memory cells further comprises recording a level of resistance.

Assignments (15)