Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region
View Patent ↗A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.
1. A method of forming a semiconductor memory cell, comprising:
forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type and the trench includes a sidewall;
modifying a shape of the trench sidewall so that the trench sidewall meets the substrate surface at an acute angle to form a sharp edge;
forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along the trench sidewall and a second portion that extends substantially along the substrate surface;
forming an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion; and
forming an electrically conductive control gate disposed over and insulated from the channel region second portion;
wherein the channel region first and second portions are non-linear with respect to each other, with the channel region second portion extending from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.
2. The method of claim 1 , further comprising:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate.
3. The method of claim 2 , wherein the formation of the conductive material block includes forming the conductive material block in electrical contact with the first region.
4. The method of claim 1 , further comprising:
forming a spacer of insulating material that is disposed between the control gate and the block of conductive material, and is disposed over the floating gate.
5. The method of claim 1 , wherein:
the formation of the floating gate includes forming an upper portion of the floating gate that terminates in an edge; and
the formation of the control gate includes forming an edge on the control gate that faces the floating gate edge.
6. The method of claim 5 , wherein:
the formation of the floating gate further includes forming the floating gate upper portion to extend above the substrate surface; and
the formation of the control gate includes:
forming a first portion of the control gate that is disposed laterally adjacent to and insulated from the floating gate upper portion, and
forming a second portion of the control gate that is disposed over and insulated from the floating gate upper portion.
7. The method of claim 1 , wherein the formation of the control gate includes:
forming a layer of polysilicon over and insulated from the substrate;
forming a layer of metalized polysilicon on the layer of polysilicon;
forming a spacer of material over the layers of polysilicon and metalized polysilicon, leaving portions of the layers of polysilicon and metalized polysilicon exposed; and
performing an etch process that removes the exposed portions of the layers of polysilicon and metalized polysilicon.
8. The method of claim 1 , wherein the channel region includes a third portion extending substantially along at least a portion of a bottom surface of the trench, and wherein the floating gate is disposed over and insulated from the channel region third portion.
9. The method of claim 1 , wherein the modification of the trench sidewall includes:
forming a first oxide layer on the trench sidewall via silicon oxidation;
removing the first oxide layer; and
forming a second oxide layer on the trench sidewall via silicon oxidation.
10. The method of claim 9 , wherein the formation of the first and second oxide layers causes the trench sidewall to meet the substrate surface at an angle substantially less than 90 degrees.
11. A method of forming an array of electrically programmable and erasable memory devices, comprising:
forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type; and
forming a plurality of pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs includes:
forming a trench into the surface of the substrate, wherein the trench has a pair of opposing sidewalls,
modifying a shape of the trench sidewalls so that the trench sidewalls meet the substrate surface at an acute angle to form a pair of sharp edges,
forming a first region in the substrate and underneath the trench,
forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate,
forming a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions, and
forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions,
wherein for each of the channel regions, the channel region first and second portions are non-linear with respect to each other, with the channel region second portion extending from one of the second regions in a direction toward one of the sharp edges and one of the floating gates to define a path for programming the one floating gate with electrons via hot electron injection.
12. The method of claim 11 , wherein the formation of each of the memory cell pairs further comprises:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the pair of floating gates.
13. The method of claim 12 , wherein the formation of the conductive material blocks includes forming each of the conductive material blocks in electrical contact with one of the first regions.
14. The method of claim 13 , wherein the formation of the conductive material blocks further includes forming a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the conductive material blocks from each of the active regions.
15. The method of claim 12 , further comprising:
forming a plurality of spacers of insulating material, wherein each of the spacers is formed between one of the blocks of conductive material and one of the control gates, and over one of the floating gates.
16. The method of claim 11 , wherein:
the formation of each of the floating gates includes forming an upper portion of the floating gate that terminates in an edge; and
the formation of each of the control gates includes forming an edge on the control gate that faces one of the floating gate edges.
17. The method of claim 16 , wherein:
each of the floating gate upper portions extend above the substrate surface; and
the formation of each of the control gates includes:
forming a first portion of the control gate that is disposed laterally adjacent to and insulated from one of the floating gate upper portions, and
forming a second portion of the control gate that is disposed over and insulated from one of the floating gate upper portions.
18. The method of claim 11 , wherein the formation of each of the control gates includes:
forming a layer of polysilicon over and insulated from the substrate;
forming a layer of metalized polysilicon on the layer of polysilicon;
forming a spacer of material over the layers of polysilicon and metalized polysilicon, leaving portions of the layers of polysilicon and metalized polysilicon exposed; and
performing an etch process that removes the exposed portions of the layers of polysilicon and metalized polysilicon.
19. The method of claim 11 , wherein each of the channel regions includes a third portion extending substantially along at least a portion of a bottom surface of one of the trenches, wherein each of the floating gates is disposed over and insulated from one of the channel region third portions.
20. The method of claim 11 , wherein the modification of the trench sidewalls includes:
forming a first oxide layer on the trench sidewalls via silicon oxidation;
removing the first oxide layer; and
forming a second oxide layer on the trench sidewalls via silicon oxidation.
21. The method of claim 20 , wherein the formation of the first and second oxide layers causes the trench sidewalls to meet the substrate surface at an angle substantially less than 90 degrees.
22. The method of claim 11 , wherein the formation of the control gates further includes forming a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
23. The method of claim 11 , wherein for each of the memory cell pairs, the formation of the pair of floating gates in the trench includes:
forming a block of conductive material in the trench;
forming a pair of spacers of material over the block of conductive material, wherein the pair of spacers leave a portion of the block of conductive material exposed;
performing an etch process that removes the exposed portion of conductive material block and leaves portions of the conductive material block underneath the pair of spacers that constitute the pair of floating gates.