Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling
View Patent ↗A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.
1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type;
first and second spaced-apart regions of a second conductivity type formed in the substrate, with a channel region therebetween;
an electrically conductive floating gate disposed vertically over and insulated from a portion of said channel region and a portion of the first region;
an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the floating gate, and an upper portion that extends up and over the floating gate and terminates in a first end that is disposed vertically over and insulated from the floating gate;
an electrically conductive control gate having a first portion and a second portion, the first control gate portion being disposed laterally adjacent to and insulated from the floating gate, and the second control gate portion extends up and over the floating gate and terminates in a second end that is disposed vertically over and insulated from the floating gate;
wherein the first and second ends are disposed laterally adjacent to and insulated from each other such that no portion of the control sate is disposed directly between the floating gate and the source region; and
an insulation material disposed directly between the floating gate and the second end, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
2. The device of claim 1 , wherein the source region upper portion has a greater width than that of the source region lower portion.
3. The device of claim 2 , wherein the source region has a substantially T-shaped cross-section.
4. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and
each of the active regions including a column of pairs of memory cells extending in the first direction, each of the memory cell pairs including:
a first region and a pair of second regions spaced apart in the substrate and having a second conductivity type, with channel regions formed in the substrate between the first region and the second regions,
a pair of electrically conductive floating gates each disposed vertically over and insulated from portion of on of the channel regions and a portion of the first region,
an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the pair of floating gates, and an upper portion that extends up and over the floating gates and terminates in a pair of first ends that each is disposed vertically over and insulated from one of the floating gates,
a pair of electrically conductive control gates each having a first portion and a second portion, wherein for each of the control gates, the first control gate portion is disposed laterally adjacent to and insulated from one of the floating gates and the second control gate portion extends up and over the one floating gate and terminates in a second end that is disposed vertically over and insulated from the one floating gate;
wherein each of the first ends is disposed laterally adjacent to and insulated from one of the second ends such that no portion of the control gates is disposed directly between the floating gates and the source region, and
an insulation material disposed directly between the floating gates and the second ends, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
5. The device of claim 4 , wherein each of the source regions extends across the active regions and isolation regions in a second direction substantially perpendicular to the first direction and intercepts one of the memory cell pairs in each of the active regions.
6. The device of claim 4 , wherein each of the control gates extends across the active regions and isolation regions in a second direction subtantially perpendicular to the first direction and intercepts one of the memory cell pairs in each of the active regions.
7. The device of claim 4 , wherein the source region upper portion has a greater width than that of the source region lower portion.
8. The device of claim 7 , wherein the source region has a substantially T-shaped cross-section.