Fast voltage regulators for charge pumps
View Patent ↗A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
1. A voltage regulator comprising:
first, second, third, fourth, and fifth transistors, each transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said gate and first terminal of the first transistor being coupled to a first voltage terminal, said second terminal of the first transistor being coupled to the second terminal of the second transistor and the gate of the third transistor, and said gate and said first terminal of the fifth transistor being coupled to the first terminal of the third transistor, such that the second transistor is configured to charge back a pumped output into said gate of the third transistor; wherein said second terminal of the third transistor being coupled to the first terminal of the fourth transistor, and said second terminal of the fourth transistor being coupled to a ground terminal, such that the third transistor and the fourth transistor are connected in series between the output terminal and ground;
an inductor including a first terminal coupled to a second voltage terminal and including a second terminal coupled to the first terminal of the third transistor and coupled to the gate and first terminal of the fifth transistor;
a capacitor including a first terminal coupled to the gate and first terminal of the second transistor, to the second terminal of the fifth transistor and to the output terminal; and
a control circuit including an input coupled to the output terminal and including an output coupled to the gate of the fourth transistor.
2. The voltage regulator of claim 1 further comprising a boost circuit coupled to the output terminal.
3. The voltage regulator of claim 1 further comprising a capacitor divider coupled to the output terminal to regulate said output voltage.
4. The voltage regulator of claim 3 wherein ratio of capacitance values of capacitors in the capacitance divider are set to avoid current consumption.
5. The voltage regulator of claim 1 wherein a push-pull source follower stage is connected to the output terminal.
6. The voltage regulator of claim 1 wherein the output is provided as a function of a ratio of a divided voltage controlled by the voltage regulator compared against a stable voltage.
7. The voltage regulator of claim 1 wherein the capacitor includes a second terminal coupled to a ground terminal.
8. The voltage regulator of claim 7 further comprising a boost circuit coupled to the output terminal.
9. The voltage regulator of claim 7 further comprising a capacitor divider coupled to the output terminal to regulate said output voltage.
10. The voltage regulator of claim 9 wherein ratio of capacitance values of capacitors in the capacitance divider are set to avoid current consumption.
11. The voltage regulator of claim 7 wherein a push-pull source follower stage is connected to the output terminal.
12. The voltage regulator of claim 7 wherein the output is provided as a function of a ratio of a divided voltage controlled by the voltage regulator compared against a stable voltage.
13. A voltage regulator comprising:
first, second, third, fourth, and fifth transistors, each transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said gate and first terminal of the first transistor being coupled to a first voltage terminal, said second terminal of the first transistor being coupled to the second terminal of the second transistor and the gate of the third transistor, said second terminal of the third transistor being coupled to the first terminal of the fourth transistor, said second terminal of the fourth transistor being coupled to a ground terminal;
an inductor including a first terminal coupled to a second voltage terminal and including a second terminal coupled to the first terminal of the third transistor and coupled to the gate and first terminal of the fifth transistor;
a capacitor including a first terminal coupled to the gate and first terminal of the second transistor, to the second terminal of the fifth transistor and to an output terminal; and
a control circuit including an input coupled to the output terminal and including an output coupled to the gate of the fourth transistor;
wherein the capacitor includes a second terminal coupled to a negative terminal of the output node, such that the negative terminal may be driven to VDD.
14. The voltage regulator of claim 13 further comprising a boost circuit coupled to the output terminal.
15. The voltage regulator of claim 13 further comprising a capacitor divider coupled to the output terminal to regulate said output voltage.
16. The voltage regulator of claim 15 wherein ratio of capacitance values of capacitors in the capacitance divider are set to avoid current consumption.
17. The voltage regulator of claim 13 wherein a push-pull source follower stage is connected to the output terminal.
18. The voltage regulator of claim 13 wherein the output is provided as a function of a ratio of a divided voltage controlled by the voltage regulator compared against a stable voltage.
19. The voltage regulator of claim 13 wherein the control circuit provides a clock signal to modulate the gate of the fourth transistor.
20. The voltage regulator of claim 19 wherein the control circuit is configured to modulate the clock signal applied to the gate of the fourth transistor via a spread spectrum technique to reduce electromagnetic interference.
21. The voltage regulator of claim 19 wherein the control circuit is configured to modulate frequency of the clock signal applied to the gate of the fourth transistor via a dithering technique to reduce electromagnetic interference.
22. The voltage regulator of claim 13 wherein the capacitor includes a second terminal coupled to a ground terminal.
23. The voltage regulator of claim 22 further comprising a boost circuit coupled to the output terminal.