Dynamically tunable resistor or capacitor using a non-volatile floating gate memory cell
View Patent ↗An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be changed by the amount of charge stored on the floating gate which affects the resistance or the capacitance of the channel from which the floating gate is spaced apart. A particular application of the programmable resistor/capacitor is used in a system whereby the resistance or the capacitance can be change or fine tuned as a result of either drift caused by time or by operating conditions such as temperature. Thus, the temperature of the substrate in which the floating gate memory cell is fabricated can be monitored and the resistance or the capacitance of the floating gate memory cell changed dynamically.
1. A programmable resistor comprising:
a first resistor having a first end connectable to a first voltage source, and a second end connected to a node;
a non-volatile floating gate memory cell having a first and a second region in a semiconductor substrate with a channel therebetween, a floating gate positioned adjacent to and spaced apart from at least a portion of said channel, wherein charges stored on said floating gate for controlling the resistance of said channel, and a control gate;
wherein said first region is connected to said node, and said second region is connectable to a second voltage source; and
a programming/erasing circuit connected to said memory cell for changing the charges stored in said floating gate thereby changing the resistance of said channel;
wherein said node provides a desired resistance.
2. The programmable resistor of claim 1 further comprising:
a switch for isolating said memory cell from said node during a programming/erasing operation.
3. The programmable resistor of claim 1 wherein said programming/erasing circuit is responsive to the output of a sensor.
4. The programmable resistor of claim 3 wherein said sensor is a temperature sensor for measuring the temperature of said substrate.
5. The programmable resistor of claim 1 , wherein said control gate is positioned adjacent to and spaced apart from said second region and another portion of said channel for controlling the resistance of said channel;
wherein said floating gate is capacitively coupled to said first region;
wherein said memory cell is programmed by electrons traversing from said second region to said first region and are injected onto the floating gate; and
wherein said memory cell is erased by Fowler Nordheim tunneling of electrons from said floating gate to said control gate.
6. A programmable capacitor comprising:
a first capacitor having a first end connected to a first node, and a second end connected to a second node;
a non-volatile floating gate memory cell having a first and a second region in a semiconductor substrate with a channel therebetween, a floating gate positioned adjacent to and spaced apart from at least a portion of said channel, wherein charges stored on said floating gate for controlling the capacitance of said channel between said first and second regions, and a control gate;
wherein said first region is connected to said first end and said second region is connected to said second end; and
a programming/erasing circuit connected to said memory cell for changing the charges stored on said floating gate thereby changing the capacitance between said first and second regions;
wherein said first end and second end provides a desired capacitance.
7. The programmable capacitor of claim 6 further comprising:
a switch for isolating said memory cell from said first end and second end during a programming/erasing operation.
8. The programmable capacitor of claim 6 wherein said programming/erasing circuit is responsive to the output of a sensor.
9. The programmable capacitor of claim 8 wherein said sensor is a temperature sensor for measuring the temperature of said substrate.
10. The programmable capacitor of claim 1 , wherein said control gate is positioned adjacent to and spaced apart from said second region and another portion of said channel for controlling the capacitance of said channel;
wherein said floating gate is capacitively coupled to said first region;
wherein said memory cell is programmed by electrons traversing from said second region to said first region and are injected onto the floating gate; and
wherein said memory cell is erased by Fowler Nordheim tunneling of electrons from said floating gate to said control gate.
11. A programmable resistor/capacitor comprising:
a non-volatile floating gate memory cell having a first and a second region in a semiconductor substrate with a channel therebetween, a floating gate positioned adjacent to and spaced apart from at least a portion of said channel, wherein charges stored on said floating gate for controlling the resistance/capacitance of said channel between said first and second regions, and a control gate; said cell having a terminal for outputting the resistance/capacitance of said cell;
a programming/erasing/reading controller circuit connected to said control gate, and said first and second regions of said cell for controlling the operation of said cell;
a pre-set store for outputting a pre-set resistance/capacitance value; and
a comparator for receiving as one input thereof the output from said terminal and for receiving as another input the output from said pre-set store and for comparing same; said comparator for activating said programming/erasing/reading controller circuit to change the amount of charges stored on said floating gate to change said resistance/capacitance of said cell in the event said output from said terminal differs from said output from said pre-set store.
12. The programmable resistor/capacitor of claim 11 wherein said comparator is activated upon power up.
13. The programmable resistor/capacitor of claim 11 wherein said comparator is activated upon system re-set.
14. The programmable resistor/capacitor of claim 11 wherein said comparator is activated upon an interrupt.
15. The programmable resistor/capacitor of claim 11 wherein said programmable resistor/capacitor is a programmable capacitor further comprising:
a first capacitor having a first end connected to a first node, and a second end connected to a second node;
said first region of said memory cell connected to said first end, and said second region of said memory cell is connected to said second end;
wherein said first end and second end provides a desired capacitance.
16. The programmable capacitor of claim 15 further comprising:
a switch for isolating said memory cell from said first end and second end during a programming/erasing operation.
17. The programmable resistor/capacitor of claim 11 wherein said programmable resistor/capacitor is a programmable resistor further comprising:
a first resistor having a first end connectable to a first voltage source, and a second end connected to a node;
said first region of said cell is connected to said node, and said second region of said cell is connectable to a second voltage source; and
wherein said node provides a desired resistance.
18. The programmable resistor of claim 17 further comprising:
a switch for isolating said memory cell from said node during a programming/erasing operation.