Low voltage, low power bandgap circuit
View Patent ↗A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.
1. A bandgap voltage generating circuit for generating a bandgap voltage, said circuit comprising:
an operational amplifier having two inputs and an output;
a current mirror circuit having at least two parallel current paths, each of said current paths controlled by a signal from said output of said operational amplifier;
one of said current paths comprising two parallel subpaths with each subpath connected to a different one of the two inputs of the operational amplifier;
a resistor divide circuit connected to another of said current paths, said resistor divide circuit providing said bandgap voltage;
wherein one of the subpaths has a resistor connected in the subpath;
wherein each current path comprises a PMOS transistor controlling current between a source and a drain of the PMOS transistor with its gate coupled to the output of the operational amplifier and a bipolar transistor having an emitter/collector connected in series with the source/drain of the PMOS transistor;
wherein each of the subpaths has a current source;
wherein the current source in each subpath comprises a PMOS transistor and a native MOS transistor connected in parallel.
2. The voltage generating circuit of claim 1 wherein each of said PMOS transistors and native NMOS transistors have a gate with a control bias to simulate a pre-determined resistance value.
3. The voltage generating circuit of claim 1 wherein said resistor divide circuit comprises a first resistor and a second resistor connected in series at a node, with said node providing said bandgap voltage.
4. The voltage generating circuit of claim 3 wherein said first resistor and second resistor have substantially equal resistance values.
5. The voltage generating circuit of claim 1 wherein the resistor divide circuit is in parallel to one of the bipolar transistors.
6. The voltage generating circuit of claim 1 further comprising a third current path having a PMOS transistor connected to said bandgap voltage, with a gate of said PMOS transistor of the third current path coupled to the output of the operational amplifier.
7. The voltage generating circuit of claim 6 wherein said resistor divide circuit comprises a first resistor and a second resistor connected in series at a node, with said node providing the bandgap voltage, with said node connected to the PMOS transistor of the third current path.
8. The voltage generating circuit of claim 1 further comprising an operational amplifier bias current circuit connected to receive the output of the operational amplifier and for providing an operational amplifier biasing current to the operational amplifier.
9. The voltage generating circuit of claim 8 wherein said operational amplifier bias current circuit comprises a PMOS transistor having a gate connected to the output of the operational amplifier, and serially connected to a NMOS transistor connected to ground.
10. The voltage generating circuit of claim 8 further comprising an initial bias current circuit connected to the operational amplifier for reducing the operational amplifier bias current to the operational amplifier as the operational amplifier bias current circuit provides the operational amplifier bias current to the operational amplifier.
11. The voltage generating circuit of claim 1 wherein the operational amplifier is a two stage operational amplifier.
12. The voltage generating circuit of claim 11 wherein one of the two stages of the operational amplifier comprises native MOS transistors.
13. The voltage generating circuit of claim 12 wherein said native MOS transistors of the one of the two stages of the operational amplifier are in one of said two inputs to the operational amplifier.
14. The voltage generating circuit of claim 12 wherein said native MOS transistors of the one of the two stages of the operational amplifier are in the output of the operational amplifier.
15. The voltage generating circuit of claim 12 wherein said operational amplifier is a cascode operational amplifier.
16. The voltage generating circuit of claim 12 wherein a first stage of the operational amplifier is a folded cascode operational amplifier.
17. The voltage generating circuit of claim 16 wherein a second stage of the operational amplifier is a common source amplifier.