IP Library Granted Patent US 7,012,273
Granted Patent B2
US 7,012,273 · App. 10/641,431 · Granted Mar 14, 2006

Phase change memory device employing thermal-electrical contacts with narrowing electrical current paths

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Quick Facts
Patent No.
US 7,012,273
App. No.
10/641,431
Granted
Mar 14, 2006
Kind
B2
Abstract

A phase changing memory device, and method of making the same, that includes contact holes formed in insulation material that extend down to and exposes source regions for adjacent FET transistors. Spacer material is disposed in the holes with surfaces that define openings each having a width that narrows along a depth of the opening. Lower electrodes are disposed in the holes. A layer of phase change memory material is disposed along the spacer material surfaces and along at least a portion of the lower electrodes. Upper electrodes are formed in the openings and on the phase change memory material layer. For each contact hole, the upper electrode and phase change memory material layer form an electrical current path that narrows in width as the current path approaches the lower electrode, such that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the upper and lower electrodes.

Claims (90)

1. A phase change memory device comprising:

a substrate;

insulation material formed over the substrate and including a hole formed therein;

spacer material disposed in the hole and having a surface that defines an opening having a width that narrows along a depth of the opening;

a first block of conductive material disposed in the hole and having an upper surface;

a layer of phase change memory material disposed in the opening and extending along the spacer material surface and at least a portion of the first block of conductive material upper surface; and

a second block of conductive material disposed in the opening and on the phase change memory material layer;

wherein the second block of conductive material and the layer of phase change memory material form an electrical current path that narrows in width as the current path approaches the first block of conductive material upper surface, so that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the first and second blocks;

wherein the substrate is semiconductor material having a first conductivity type, and the memory device further comprises:

first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region defined in the substrate therebetween; and

a third block of conductive material disposed over and insulated from the substrate including the channel region;

wherein the first block is disposed over and electrically connected to the first region.

2. A phase change memory device comprising:

a substrate;

insulation material formed over the substrate and including a hole formed therein;

spacer material disposed in the hole and having a surface that defines an opening having a width that narrows along a depth of the opening;

a first block of conductive material disposed in the hole and having an upper surface;

a layer of phase change memory material disposed in the opening and extending along the spacer material surface and at least a portion of the first block of conductive material upper surface; and

a second block of conductive material disposed in the opening and on the phase change memory material layer;

wherein the second block of conductive material and the layer of phase change memory material form an electrical current path that narrows in width as the current path approaches the first block of conductive material upper surface, so that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the first and second blocks;

wherein the spacer material is formed over the first block of conductive material upper surface.

3. The phase change memory device of claim 2 , wherein the spacer material surface is generally funnel-shaped.

4. The phase change memory device of claim 2 , wherein the current path reaches a minimum cross sectional area adjacent the first block of conductive material upper surface.

5. A phase change memory device comprising:

a substrate;

insulation material formed over the substrate and including a hole formed therein;

spacer material disposed in the hole and having a surface that defines an opening having a width that narrows along a depth of the opening;

a first block of conductive material disposed in the hole and having an upper surface;

a layer of phase change memory material disposed in the opening and extending along the spacer material surface and at least a portion of the first block of conductive material upper surface; and

a second block of conductive material disposed in the opening and on the phase change memory material layer;

wherein the second block of conductive material and the layer of phase change memory material form an electrical current path that narrows in width as the current path approaches the first block of conductive material upper surface, so that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the first and second blocks;

wherein the spacer material is formed over the first block of conductive material upper surface;

wherein an indentation is formed into the first block of conductive material upper surface, and a portion of the phase change memory material layer extends into the indentation.

6. The phase change memory device of claim 5 , wherein a portion of the second block extends into the indentation.

7. A phase change memory device comprising:

a substrate;

insulation material formed over the substrate and including a hole formed therein;

spacer material disposed in the hole and having a surface that defines an opening having a width that narrows along a depth of the opening;

a first block of conductive material disposed in the hole and having an upper surface;

a layer of phase change memory material disposed in the opening and extending along the spacer material surface and at least a portion of the first block of conductive material upper surface; and

a second block of conductive material disposed in the opening and on the phase change memory material layer;

wherein the second block of conductive material and the layer of phase change memory material form an electrical current path that narrows in width as the current path approaches the first block of conductive material upper surface, so that electrical current passing through the current path generates heat for heating the phase change memory material disposed between the first and second blocks;

wherein a lower portion of the phase change memory material layer merges together to form a column of the phase change memory material disposed directly over the first block of conductive material upper surface.

8. The phase change memory device of claim 7 , wherein the first block of conductive material is disposed in the opening defined by the spacer material surface.

9. The phase change memory device of claim 7 , wherein the current path reaches a minimum cross sectional area at the column.

10. An array of phase change memory devices, comprising:

a substrate;

insulation material formed over the substrate and including a plurality of holes formed therein;

spacer material disposed in each of the holes and having surfaces that define openings having widths that narrow along depths of the openings;

a plurality of first blocks of conductive material each disposed in one of the holes and having an upper surface;

phase change memory material that extends along the spacer material surfaces and at least a portion of the first block of conductive material upper surfaces; and

a plurality of second blocks of conductive material each disposed in one of the openings and on the phase change memory material layer;

wherein the second blocks of conductive material and the phase change memory material form electrical current paths that narrow in width as each of the current paths approaches one of the first block of conductive material upper surfaces, so that electrical current passing through the current paths generates heat for heating the phase change memory material;

wherein the substrate is semiconductor material having a first conductivity type, and the array of phase change memory devices further comprises:

a plurality of first and second spaced-apart regions formed in the substrate and having a second conductivity type, wherein channel regions of the substrate are defined between the first and second regions; and

a plurality of third blocks of conductive material disposed over and insulated from the substrate including the channel regions;

wherein the first blocks are disposed over and electrically connected to the first regions.

11. An array of of phase change memory devices, comprising:

a substrate;

insulation material formed over the substrate and including a plurality of holes formed therein;

spacer material disposed in each of the holes and having surfaces that define openings having widths that narrow along depths of the openings;

a plurality of first blocks of conductive material each disposed in one of the holes and having an upper surface;

phase change memory material that extends along the spacer material surfaces and at least a portion of the first block of conductive material upper surfaces; and

a plurality of second blocks of conductive material each disposed in one of the openings and on the phase change memory material layer;

wherein the second blocks of conductive material and the phase change memory material form electrical current paths that narrow in width as each of the current paths approaches one of the first block of conductive material upper surfaces, so that electrical current passing through the current paths generates heat for heating the phase change memory material;

wherein the spacer material is formed over the first block of conductive material upper surfaces.

12. The array of claim 11 , wherein the spacer material surfaces are generally funnel-shaped.

13. The array of claim 11 , wherein the current paths reach minimum cross sectional areas adjacent to the first block of conductive material upper surfaces.

14. An array of phase change memory devices, comprising:

a substrate;

insulation material formed over the substrate and including a plurality of holes formed therein;

spacer material disposed in each of the holes and having surfaces that define openings having widths that narrow along depths of the openings;

a plurality of first blocks of conductive material each disposed in one of the holes and having an upper surface;

phase change memory material that extends along the spacer material surfaces and at least a portion of the first block of conductive material upper surfaces; and

a plurality of second blocks of conductive material each disposed in one of the openings and on the phase change memory material layer;

wherein the second blocks of conductive material and the phase change memory material form electrical current paths that narrow in width as each of the current paths approaches one of the first block of conductive material upper surfaces, so that electrical current passing through the current paths generates heat for heating the phase change memory material;

wherein the spacer material is formed over the first block of conductive material upper surface;

wherein indentations are formed into the first block of conductive material upper surfaces, and portions of the phase change memory material extend into the indentations.

15. The array of claim 14 , wherein portions of the second blocks extend into the indentations.

16. An array of of phase change memory devices, comprising:

a substrate;

insulation material formed over the substrate and including a plurality of holes formed therein;

spacer material disposed in each of the holes and having surfaces that define openings having widths that narrow along depths of the openings;

a plurality of first blocks of conductive material each disposed in one of the holes and having an upper surface;

phase change memory material that extends along the spacer material surfaces and at least a portion of the first block of conductive material upper surfaces; and

a plurality of second blocks of conductive material each disposed in one of the openings and on the phase change memory material layer;

wherein the second blocks of conductive material and the phase change memory material form electrical current paths that narrow in width as each of the current paths approaches one of the first block of conductive material upper surfaces, so that electrical current passing through the current paths generates heat for heating the phase change memory material;

wherein the phase change memory material includes at least one layer of material having a lower portion that merges together to form columns of the phase change memory material disposed directly over the first block of conductive material upper surfaces.

17. The array of claim 16 , wherein the first blocks of conductive material are disposed in the openings defined by the spacer material surfaces.

18. The array of claim 16 , wherein the current paths reach minimum cross sectional areas at the columns.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 059687/0344 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: SILICON STORAGE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0316 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2004
From: CHEN, BOMY
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 014884/0408 →