Method of testing data retention of a non-volatile memory cell having a floating gate
View Patent ↗A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.
1. A method of testing a non-volatile memory cell having a floating gate for the storage of charges thereon, wherein said method for testing the memory cell in the event the memory cell has a leakage current from the floating gate which is dependent upon the absolute value of the voltage of the floating gate, wherein said cell is characterized by a first erase voltage, a first programming voltage and a first read voltage, applied during normal operation, and a first read current of an erased memory cell, detected during normal operation, wherein said method comprising:
applying a voltage greater than the first erase voltage to over erase the floating gate;
subjecting the memory cell including the floating gate to a single high temperature bake; and
testing the data retention of the floating gate by applying a read voltage lower than the first read voltage.
2. The method of claim 1 wherein said memory cell is characterized by:
a single crystalline substrate of a first conductivity type and having a top surface;
a first region of a second conductivity type in said substrate along the top surface;
a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;
a channel region between the first region and the second region;
a word line gate positioned over a first portion of the channel region, spaced apart from the channel region by a first insulating layer;
a floating gate positioned over another portion of the channel region, adjacent to and separated from the word line gate, wherein the floating gate is separated from the channel region by a second insulating layer;
a coupling gate positioned over the floating gate and insulated therefrom by a third insulating layer; and
an erase gate, positioned adjacent to the floating gate and on a side opposite to the word line gate; said erase gate positioned over the second region and is insulated therefrom.
3. The method of claim 2 wherein said testing step determines the memory cell is defective in the event the read current of the memory cell after said subjecting step is lower than a read reference current.
4. A method of testing a non-volatile memory cell having a floating gate for the storage of charges thereon, wherein said method for testing the memory cell in the event the memory cell has a leakage current from the floating gate which is dependent upon the absolute value of the voltage of the floating gate, wherein said cell is characterized by a first erase voltage, a first programming voltage and a first read voltage, applied during normal operation, and a first read current of a programmed memory cell, detected during normal operation, wherein said method comprising:
applying a voltage greater than the first programming voltage to over program the floating gate;
subjecting the memory cell including the floating gate to a single high temperature bake; and
testing the data retention of the floating gate by applying a read voltage greater than the first read voltage.
5. The method of claim 4 wherein said memory cell is characterized by:
a single crystalline substrate of a first conductivity type and having a top surface;
a first region of a second conductivity type in said substrate along the top surface;
a second region of the second conductivity type, in said substrate along the top surface, spaced apart from the first region;
a channel region between the first region and the second region;
a word line gate positioned over a first portion of the channel region, spaced apart from the channel region by a first insulating layer;
a floating gate positioned over another portion of the channel region, adjacent to and separated from the word line gate, wherein the floating gate is separated from the channel region by a second insulating layer;
a coupling gate positioned over the floating gate and insulated therefrom by a third insulating layer; and
an erase gate, positioned adjacent to the floating gate and on a side opposite to the word line gate; said erase gate positioned over the second region and is insulated therefrom.
6. The method of claim 5 wherein said testing step determines the memory cell is defective in the event the read current of the memory cell after said subjecting step is higher than a read reference current.