Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array
View Patent ↗A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
1. An array of Read Only Memory (ROM) cells, each cell for storing one of n (n>2) possible states, said array comprising:
a semiconductor substrate of a first conductivity type having a first concentration;
an array of ROM cells arranged in a plurality of rows and columns in said substrate;
each ROM cell having a first region of a second conductivity type in said substrate different from said first conductivity type; a second region of said second conductivity type in said substrate, spaced apart from said first region; a channel between said first region and said second region; said channel having three portions: a first, a second and a third portion; a gate spaced apart and insulated from at least said second portion of said channel; said ROM cell being in one of a plurality of n (n>2) possible states, characterized by:
(a) a first extension region in said first portion of said channel adjacent to said first region, with said first extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said third portion of said channel adjacent to said second region being said first conductivity type having said first concentration; or
(b) a second extension region in said third portion of said channel adjacent to said second region, with said second extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said first portion of said channel adjacent to said first region being said first conductivity type having said first concentration; or
(c) said first extension region in said first portion of said channel adjacent to said first region, with said first extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said second extension region in said third portion of said channel adjacent to said second region with said second extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration; or
(d) said first portion of said channel adjacent to said first region being said first conductivity type having said first concentration, and said third portion of said channel adjacent to said second region being said first conductivity type having said first concentration;
said array of ROM cells arranged with ROM cells in the same row having their gates connected in common;
said array of ROM cells arranged with ROM cells in the same column having their first regions connected in common, and second regions connected in common, with each pair of columns of adjacent ROM cells sharing a common first region; and
wherein said one of a plurality of n (n<2) possible states of each ROM cell is determined by supplying a first voltage to said gate; a second voltage to said first region and a third voltage to said second region; and measuring a first current flowing from said second region to said first region; and supplying said first voltage to said gate; a second voltage to said second region and a third voltage to said first region; and measuring a second current flowing from said first region to said second region; and determining said one state based upon said first current measured and said second current measured.
2. The array of claim 1 further comprising a MOS transistor in said substrate, said MOS transistor formed during a masking operation; and
wherein each of said ROM cells in said array being in one of a plurality of n (n<2) states formed during said masking operation.
3. The array of claim 1 further comprising
a voltage source for supplying a first voltage, a second voltage and a third voltage;
a switch for connecting said first voltage to a selected row to said gate, for connecting said second voltage to a selected first column to said first region, and for connecting said third voltage to a selected second column to said second region; and for connecting said second voltage to said selected second column, and said third voltage to said selected first column.
4. The array of claim 3 further comprising:
a sensing circuit for determining current flow; and
said switch for connecting said sensing circuit to said selected first column to measure said first current; and for connecting said sensing circuit to said selected second column to measure said second current.
5. The array of claim 1 wherein each of said first and second extension regions is of said second conductivity type.
6. The array of claim 1 wherein each of said first and second extension regions is of said first conductivity type, having a concentration greater than said first concentration.
7. An integrated circuit device comprising:
a semiconductor substrate of a first conductivity type having a first concentration;
an array of Read Only Memory (ROM) cells, each ROM cell having one of a plurality of n (n>2) possible states formed during a masking operation; said cell comprising:
a first region of a second conductivity type in said substrate different from said first conductivity type;
a second region of said second conductivity type in said substrate, spaced apart from said first region;
a channel between said first region and said second region; said channel having three portions: a first, a second and a third portion;
a gate spaced apart and insulated from at least said second portion of said channel;
each of said ROM cells being in one of said n possible states characterized by:
(a) a first extension region in said first portion of said channel adjacent to said first region, with said first extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said third portion of said channel adjacent to said second region being said first conductivity type having said first concentration; or
(b) a second extension region in said third portion of said channel adjacent to said second region, with said second extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said first portion of said channel adjacent to said first region being said first conductivity type having said first concentration; or
(c) said first extension region in said first portion of said channel adjacent to said first region, with said first extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration, and said second extension region in said third portion of said channel adjacent to said second region with said second extension region being of said second conductivity type or being of said first conductivity type having a concentration different from said first concentration; or
(d) said first portion of said channel adjacent to said first region being said first conductivity type having said first concentration, and said third portion of said channel adjacent to said second region being said first conductivity type having said first concentration;
said array of ROM cells arranged with ROM cells in the same row having their gates connected in common;
said array of ROM cells arranged with ROM cells in the same column having their first regions connected in common, and second regions connected in common, with each pair of columns of adjacent ROM cells sharing a common first region; and
wherein said one of a plurality of n (n>2) states of each ROM cell is determined by supplying a first voltage to said gate; a second voltage to said first region and a third voltage to said second region; and measuring a first current flowing from said second region to said first region; and supplying said first voltage to said gate; a second voltage to said second region and a third voltage to said first region; and measuring a second current flowing from said first region to said second region; and determining said one state based upon said first current measured and said second current measured.
8. The array of claim 7 further comprising
a voltage source for supplying a first voltage, a second voltage and a third voltage;
a switch for connecting said first voltage to a selected row to said gate, said second voltage to a selected first column to said first region, and said third voltage to a selected second column to said second region; and for connecting said second voltage to said selected second column, and said third voltage to said selected first column.
9. The array of claim 8 further comprising:
a sensing circuit for determining current flow;
said switch for connecting said sensing circuit to said selected first column to measure said first current; and for connecting said sensing circuit to said selected second column to measure said second current.
10. The array of claim 7 wherein each of said first and second extension regions is of said second conductivity type.
11. The array of claim 7 wherein each of said first and second extension regions is of said first conductivity type having a concentration greater than said first concentration.