Flash memory array having control/decode circuitry for disabling top gates of defective memory cells
View Patent ↗A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
1. A memory system comprising:
a plurality of memory cells arranged in sectors, each memory cell having a top gate; and
a control circuit coupled to the plurality of memory cells to detect top gates that are defective and to control the disabling of top gates that are defective.
2. The memory system of claim 1 wherein the memory cells are tip erased memory cells.
3. The memory system of claim 1 wherein the memory cells are source side injection memory cells.
4. The memory system of claim 1 wherein the memory cells are multilevel memory cells.
5. A memory system comprising:
a plurality of memory cells arranged in sectors,
a plurality of decoders coupled to the plurality of memory cells, each decoder detecting defective top gates and generating a latched signal disabling the application of low voltage signals to memory cells having a defective top gate in a corresponding sector.
6. The memory system of claim 5 wherein said latched signal is latched at power up recall.
7. The memory system of claim 5 wherein the memory cells are multilevel memory cells.
8. The memory system of claim 5 wherein each decoder includes a low voltage decoder for applying low voltage signals to memory cells in the corresponding sector.
9. The memory system of claim 8 wherein the memory cells are multilevel memory cells.
10. The memory system of claim 8 wherein each low voltage decoder includes a latch to disable said applying in response to the defective top gate.
11. The memory system of claim 8 wherein the low voltage decoder includes a current limiter on a top gate line for said memory cells.
12. The memory system of claim 11 wherein the memory cells are multilevel memory cells.
13. The memory system of claim 5 wherein each decoder includes a high voltage decoder for applying high voltage signals to memory cells in the corresponding sector.
14. The memory system of claim 13 wherein the memory cells are multilevel memory cells.
15. The memory system of claim 13 wherein each high voltage decoder includes a latch to disable said applying in response to the defective top gate.
16. The memory system of claim 15 wherein each high voltage decoder includes the latch to disable said applying in response to a defective word line.