Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture
View Patent ↗Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.
1. A flash memory structure formed on a semiconductor substrate of a first conductivity type, the structure comprising:
a non-diffused channel region within the semiconductor substrate through which electron flow may be induced by application of voltage to gate elements disposed above the channel region;
a plurality of floating gates, spaced apart from one another, each insulated from the channel region;
a plurality of T-shaped control gates, spaced apart from one another, each insulated from the channel region, each control gate being laterally adjacent a first floating gate in position across form the channel region, and being capacitively coupled to the first floating gate, wherein each control gate and the first floating gate to which the control gate is capacitively coupled form a subcell; and
a plurality of assist gates, spaced apart from one another, each insulated from the channel region, each assist gate being between and insulated from a first subcell and a second subcell, wherein each assist gate being between a floating gate in the first subcell and a floating gate in the second subcell;
wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath; and
wherein operation of the second subcell as a programmed cell is enabled via electron flow induced in the first channel region, the second channel region, and the third channel region by voltages on the first floating gate associated with the first control gate, the assist gate, and the second control gate, respectively.
2. The structure of claim 1 wherein each floating gate is between a control gate and an assist gate.
3. The structure of claim 1 wherein each floating gate within the first subcell is immediately adjacent the first channel region and each floating gate with the second subcell is immediately adjacent the second channel region.
4. The structure of claim 1 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.
5. The structure of claim 3 wherein the floating gate is disposed adjacent the substrate, a control gate, and an assist gate, and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.
6. The structure of claim 1 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
7. The structure of claim 6 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.
8. The structure of claim 7 wherein each floating gate is located between an upper portion of a control gate and the channel region.
9. The structure of claim 7 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.
10. The structure of claim 1 wherein the channel region defines a path for one or both of reading or programming a floating gate.
11. The structure of claim 1 wherein each control gate is in a trench capacitively coupled to first and second floating gates in the trench.
12. The structure of claim 11 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
13. The structure of claim 10 wherein the floating gates are positioned along sidewalls of the trenches.
14. The structure of claim 1 , each control gate being between the first floating gate and a second floating gate, and being capacitively coupled to the second floating gate, wherein each subcell further comprises the second floating gate.
15. The structure of claim 5 wherein each floating gate is between a control gate and an assist gate.
16. The structure of claim 2 wherein each floating gate within the first subcell is immediately adjacent the first channel region and each floating gate with the second subcell is immediately adjacent the second channel region.
17. The structure of claim 2 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.
18. The structure of claim 16 wherein the floating gate is disposed adjacent the substrate, a control gate, and an assist gate, and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.
19. The structure of claim 2 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
20. The structure of claim 19 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.
21. The structure of claim 20 wherein each floating gate is located between an upper portion of a control gate and the channel region.
22. The structure of claim 20 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.
23. The structure of claim 2 wherein the channel region defines a path for one or both of reading or programming a floating gate.
24. The structure of claim 2 wherein each control gate is in a trench capacitively coupled to first and second floating gates in the trench.
25. The structure of claim 24 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
26. The structure of claim 23 wherein the floating gates are positioned along sidewalls of the trenches.
27. The structure of claim 2 , each control gate being between the first floating gate and a second floating gate, and being capacitively coupled to the second floating gate, wherein each subcell further comprises the second floating gate.
28. The structure of claim 14 wherein each floating gate within the first subcell is immediately adjacent the first channel region and each floating gate with the second subcell is immediately adjacent the second channel region.
29. The structure of claim 14 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.
30. The structure of claim 3 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.
31. The structure of claim 3 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
32. The structure of claim 31 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.
33. The structure of claim 32 wherein each floating gate is located between an upper portion of a control gate and the channel region.
34. The structure of claim 32 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.
35. The structure of claim 3 wherein the channel region defines a path for one or both of reading or programming a floating gate.
36. The structure of claim 3 wherein each control gate is in a trench capacitively coupled to first and second floating gates in the trench.
37. The structure of claim 36 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
38. The structure of claim 35 wherein the floating gates are positioned along sidewalls of the trenches.
39. The structure of claim 3 , each control gate being between the first floating gate and a second floating gate, and being capacitively coupled to the second floating gate, wherein each subcell further comprises the second floating gate.
40. The structure of claim 4 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.
41. The structure of claim 4 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.
42. The structure of claim 41 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.
43. The structure of claim 42 wherein each floating gate is located between an upper portion of a control gate and the channel region.
44. The structure of claim 4 wherein the channel region defines a path for one or both of reading or programming a floating gate.
45. The structure of claim 4 wherein each control gate is in a trench capacitively coupled to first and second floating gates in the trench.
46. The structure of claim 4 , each control gate being between the first floating gate and a second floating gate, and being capacitively coupled to the second floating gate, wherein each subcell further comprises the second floating gate.