Sub volt flash memory system
View Patent ↗Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
1. A method for controlling a memory operation on a flash memory, the method comprising:
applying a preemphasis signal on a signal line coupled to a plurality of memory cells, the preemphasis signal having at least one characteristic dependent on loading of the signal line.
2. The method of claim 1 wherein the preemphasis signal on the signal line causes at least one of the plurality of memory cells to perform a memory operation.
3. The method of claim 1 wherein the loading on the signal line is a resistor-capacitor loading.
4. The method of claim 1 wherein the signal line is a bitline and the preemphasis signal drives the bitline.
5. The method of claim 1 wherein the signal line is a wordline and the preemphasis signal drives the wordline.
6. The method of claim 1 wherein the signal line is a resistance-capacitance (RC) line and the preemphasis signal drives the RC line.
7. The method of claim 1 wherein the signal line is a input/output line and the preemphasis signal drives the input/output line.
8. The method of claim 1 wherein applying a preemphasis signal includes driving a voltage on the signal line to a negative voltage level for deselection of at least one of the memory cells.
9. The method of claim 1 wherein applying a preemphasis signal includes driving a voltage on the signal line that is less than a forward bias pn junction voltage.