Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor
View Patent ↗A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.
1. A non-volatile memory cell, comprising:
a substrate material having a first conductivity type and a surface;
a trench formed into the surface of the substrate;
first and second spaced apart regions formed in the substrate and having a second conductivity type, with a channel region in the substrate therebetween, wherein the first region is formed under the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate;
a charge trapping layer in the trench adjacent to and insulated from the first portion of the channel region for controlling the conduction of the first portion of the channel region;
an electrically conductive gate in the trench, adjacent to and insulated from the charge trapping layer and from the first region and capacitively coupled to the charge trapping layer; and
an electrically conductive control gate disposed over and insulated from the second portion of the channel region only by a single insulation layer, without any conductive gate disposed between the control gate and the second portion of the channel region, for controlling the conduction of the second portion of the channel region;
wherein said charge trapping layer is in the trench and extends no higher than the single insulation layer, and wherein said conductive gate is in said trench and extends no higher than the single insulation layer.
2. The memory cell of claim 1 wherein said charge trapping layer is silicon nitride.
3. The memory cell of claim 1 wherein said control gate is only above the surface.
4. An array of non-volatile memory cells, comprising:
a substrate material having a first conductivity type and a surface;
a plurality of spaced apart trenches, substantially parallel to one another extending in a row direction, formed into the surface of the substrate;
a plurality of first regions, with each first region formed under each trench extending in the row direction with each first region being of a second conductivity type;
a plurality of second regions along the surface of the substrate between trenches, in a column direction substantially perpendicular to the row direction, with each second region forming a channel region for a memory cell between the second region and an adjacent first region; said channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate, adjacent to the second region;
a pair of charge trapping layers in the trench in each column, each charge trapping layer adjacent to and insulated from the sidewalls of the trench along the first portion of the channel region for controlling the conduction of the first portion of the channel region;
a plurality of electrically conductive gates, with a conductive gate in each trench extending in the row direction, adjacent to and insulated from the charge trapping layers of each column and from the first region and capacitively coupled to the charge trapping layers; and
a plurality of spaced apart electrically conductive control gates, parallel to one another, extending in the row direction, disposed over and insulated from the second portion of each channel region only by a single insulation layer, without any conductive gate disposed between the control gates and the second portion of the channel region, for controlling the conduction of each second portion of the channel region;
wherein said charge trapping layer is in the trench and extends no higher than the single insulation layer, and wherein said conductive gate is in said trench and extends no higher than the single insulation layer.
5. The array of claim 4 wherein said charge trapping layer is silicon nitride.
6. The array of claim 4 wherein said control gate is only above the surface.