Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same
View Patent ↗A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
1. A method of forming a semiconductor memory cell, comprising:
forming a trench into a surface of a semiconductor substrate, wherein the substrate has a first conductivity type;
forming first and second spaced-apart regions of a second conductivity type in the substrate with the first region formed underneath the trench, wherein a channel region is defined in the substrate between the first and second regions such that the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate;
forming an electrically conductive floating gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
forming an electrically conductive erase gate having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate; and
forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion.
2. The method of claim 1 , further comprising:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate.
3. The method of claim 2 , wherein the formation of the conductive material block includes forming the conductive material block in electrical contact with the first region.
4. The method of claim 1 , further comprising:
forming insulation material between the erase gate and the floating gate with a thickness that permits Fowler-Nordheim tunneling.
5. A method of forming an array of electrically programmable and erasable memory devices, comprising:
forming spaced apart isolation regions on a semiconductor substrate that are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a surface and a first conductivity type; and
forming a plurality of pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs includes:
forming a trench into the surface of the substrate having a pair of opposing sidewalls,
forming a first region in the substrate and underneath the trench,
forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate,
forming a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion,
forming a pair of electrically conductive erase gates each having at least a lower portion thereof disposed in the trench adjacent to and insulated from one of the floating gates; and
forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion.
6. The method of claim 5 , wherein the formation of each of the memory cell pairs further comprises:
forming a block of conductive material having at least a lower portion thereof disposed in the trench adjacent to and insulated from the pair of floating gates.
7. The method of claim 6 , wherein the formation of the conductive material blocks includes forming each of the conductive material blocks in electrical contact with one of the first regions.
8. The method of claim 7 , further comprising:
forming insulation material between each of the erase gates and one of the floating gates with a thickness that permits Fowler-Nordheim tunneling.
9. The method of claim 7 , wherein the formation of the control gates further includes forming a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction substantially perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
10. The method of claim 9 , wherein the formation of the conductive material blocks further includes forming a plurality of conductive source lines of conductive material each extending across the active and isolation regions in the second direction and each electrically connecting together one of the conductive material blocks from each of the active regions.
11. The method of claim 10 , wherein the formation of the erase gates further includes forming a plurality of conductive erase lines of conductive material each extending across the active and isolation regions in the second direction and each electrically connecting together one of the erase gate from each of the active regions.