Method and apparatus for inhibiting the programming of unselected bitlines in a flash memory system
View Patent ↗Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.
1. A flash memory device, comprising:
an array of flash memory cells organized into rows and columns, each column of flash memory cells coupled to a bit line;
a programming circuit coupled to the array to apply a programming current to a selected bit line; and
a programming inhibit circuit coupled to the array to apply an inhibit bias source to unselected bit lines;
wherein during a programming operation a selected cell coupled to the selected bit line is programmed but all cells coupled to the unselected bit lines are not programmed; and
wherein the programming inhibit circuit comprises:
a first set of PMOS transistors, wherein each bit line is coupled to a PMOS transistor in the first set of PMOS transistors to receive an inhibit bias source; and
a second set of PMOS transistors, wherein each PMOS transistor in the second set of PMOS transistors is coupled to a plurality of PMOS transistors in the first set of PMOS transistors to provide the inhibit bias source.
2. The flash memory device of claim 1 , wherein the inhibit bias source is a current source.
3. The flash memory device of claim 1 , wherein the inhibit bias source is a voltage source.
4. The flash memory device of claim 1 , wherein each memory cell is a source side injection flash memory cell.
5. The flash memory device of claim 1 , wherein each memory cell is a source side injection flash memory cell with tip erase.
6. The flash memory device of claim 1 , wherein the memory cells are arranged in pairs, each pair comprising two floating gates sharing an erase gate.
7. The flash memory device of claim 1 , wherein the memory cells are arranged in pairs, each pair comprising two floating gates sharing a wordline.
8. A flash memory device, comprising:
an array of flash memory cells organized into rows and columns, each column of flash memory cells coupled to a bit line;
a programming circuit coupled to the array to apply a programming current to a selected bit line, the programming circuit comprising:
a current mirror comprising a first transistor and a second transistor, the first transistor coupled to a programming current source and the second transistor coupled to the selected bit line;
a circuit for sampling a leakage current and injecting the leakage current into the selected bit line; and
a programming inhibit circuit coupled to the array to apply an inhibit bias source to unselected bit lines;
wherein during a programming operation a selected cell coupled to the selected bit line is programmed but all cells coupled to the unselected bit lines are not programmed; and
wherein the circuit for sampling a leakage current comprises a current mirror comprising a third transistor and a fourth transistor, the third transistor coupled to a dummy bitline to sample leakage current and the second transistor coupled to the selected bit line.
9. The flash memory device of claim 8 , wherein the inhibit bias source is a current source.
10. The flash memory device of claim 8 , wherein the inhibit bias source is a voltage source.
11. The flash memory device of claim 8 , wherein each memory cell is a source side injection flash memory cell.
12. The flash memory device of claim 8 , wherein each memory cell is a source side injection flash memory cell with tip erase.
13. The flash memory device of claim 8 , wherein the memory cells are arranged in pairs, each pair comprising two floating gates sharing an erase gate.
14. The flash memory device of claim 8 , wherein the memory cells are arranged in pairs, each pair comprising two floating gates sharing a wordline.