Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same
A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.
1. A method of forming a memory device, comprising:
providing a semiconductor substrate having a memory cell area, a core device area and an HV device area;
forming spaced apart source and drain regions in the memory cell area of the substrate, with a channel region extending there between;
forming a conductive floating gate disposed over and insulated from a first portion of the channel region and a portion of the source region;
forming a conductive control gate disposed over and insulated from the floating gate;
forming a first conductive layer in the memory cell area that at least extends over and is insulated from the source region and a second portion of the channel region;
forming a first insulation layer that extends over the first conductive layer in the memory cell area, a surface portion of the substrate in the core device area and a surface portion of the substrate in the HV device area;
removing the first insulation layer from the core device area;
forming an HKMG layer that extends over the first insulation layer in the memory cell area and the HV device area, and over the surface portion of the substrate in the core device area, wherein the HKMG layer includes:
a layer of high K dielectric material, and
a layer of metal material on the layer of high K dielectric material;
forming a second conductive layer that extends over the HKMG layer in the memory cell area, the core device area and the HV device area;
removing the HKMG layer and the second conductive layer from the memory cell area;
removing the first insulation layer from the memory cell area;
removing portions of the first conductive layer, wherein a first portion of the first conductive layer disposed over and insulated from the source region remains as an erase gate, and wherein second portion of the first conductive layer disposed over and insulated from a second portion of the channel region remains as a word line gate; and
removing portions of the HKMG layer and the second conductive layer from the core device area and the HV device area, wherein a first portion of the HKMG layer and a first portion of the second conductive layer remain in the core device area as a first logic gate, and wherein a second portion of the HKMG layer and a second portion of the second conductive layer remain in the HV device area as a second logic gate.
2. The method of claim 1 , wherein the first insulation layer is silicon dioxide.
3. The method of claim 1 , wherein the first and second conductive layers are polysilicon.
4. The method of claim 1 , wherein the second logic gate is insulated from the substrate by the first insulation layer and the first logic gate is not insulated from the substrate by the first insulation layer.
5. The method of claim 1 , further comprising: forming an interfacial layer of insulation material disposed between the HKMG layer and the first insulation layer in the HV device area and between the HKMG layer and the substrate in the core device area.