Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system
View Patent ↗A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.
1. A method for determining valid voltages for accessing a plurality of digital multilevel memory cells comprising:
dynamically detecting a window of valid data voltages for said plurality of digital multilevel memory cells.
2. The method of claim 1 wherein the detecting comprises:
incrementing a first programming voltage to program data in said plurality of memory cells;
verifying whether said data in at least one of said plurality of memory cell is properly programmed; and
repeating said incrementing and verifying until data is verified to be properly programmed in one of said plurality of memory cells.
3. The method of claim 2 wherein said verifying includes voltage mode sensing of the memory cells.
4. The method of claim 2 wherein said verifying includes current mode sensing of the memory cells.
5. The method of claim 2 wherein the memory cells are source side injection flash memory cells.
6. The method of claim 1 further comprising:
verifying data in each memory cell of said plurality of memory cell.
7. The method of claim 6 wherein said verifying data at each memory cell includes voltage mode sensing of the memory cells.
8. The method of claim 6 wherein said verifying data in each memory cell includes current mode sensing of the memory cells.
9. The method of claim 6 wherein the verifying data further comprises:
incrementing a second programming voltage;
verifying whether data in each memory cell is properly programmed within a margin;
repeating said incrementing and verifying for each memory cell outside of said margin.
10. The method of claim 9 wherein the margin has a upper margin and a lower margin, the upper margin being different than the lower margin.
11. The method of claim 10 wherein the verifying of said detecting is to another margin, said another margin being different than said upper and lower margins.
12. The method of claim 9 wherein the incrementing the first programming voltage includes incrementing said first programming voltage by a first incremental voltage, and wherein the incrementing the second programming voltage includes incrementing said second programming voltage by a second incremental voltage.
13. The method of claim 12 wherein the first and second incremental voltages are equal.
14. The method of claim 12 wherein the first and second incremental voltages are different.
15. A method for determining valid voltages for accessing a plurality of digital multilevel memory cells, the memory cells being arranged in sectors, the method comprising:
dynamically detecting a window of valid data voltages for one of said sectors of said plurality of digital multilevel memory cells.
16. The method of claim 15 wherein the detecting comprises:
first incrementing a first programming voltage by a first incremental voltage to program data in said sector of memory cells;
first verifying whether said data in at least one memory cells of said sector is properly programmed; and
first repeating said first incrementing and first verifying until data is verified to be properly programmed in one memory cell of said sector;
second incrementing said first programming voltage by a second incremental voltage to program data in a sector of memory cells;
second verifying whether said data in at least one memory cells of said sector is properly programmed; and
second repeating said second incrementing and second verifying until data is verified to be properly programmed in one memory cell of said sector.
17. The method of claim 16 wherein said first and second verifying each include voltage mode sensing of the memory cells.
18. The method of claim 16 wherein said first and second verifying each include current mode sensing of the memory cells.
19. The method of claim 16 wherein said memory cells are source side injection flash memory cells.
20. The method of claim 16 further comprising:
verifying data in each memory cell of said plurality of memory cells.
21. The method of claim 20 wherein the verifying data further comprises:
incrementing a second programming voltage by a third incremental voltage;
verifying whether data in each memory cell of a sector is properly programmed;
repeating said incrementing and verifying for each memory cell outside of a margin.
22. The method of claim 21 wherein the verifying of said detecting is to another margin, said another margin being different than said first and second margins.
23. The method of claim 21 wherein the first, second, and third incremental voltages are different.
24. The method for determining valid voltages for accessing a plurality of digital multilevel memory cells, the method comprising:
detecting a window of valid data voltages for said plurality of digital multilevel memory cells;
verifying and programming with incremental small changes in a programming voltage; and verifying and programming with incremental large steps in said programming voltage.
25. The method of claim 24 wherein said small steps are variable.
26. The method of claim 25 wherein said large steps are variable.
27. A method of determining valid voltages for accessing a plurality of digital multilevel cells, the method comprising:
detecting a window of valid data voltages for said plurality of digital multilevel memory cells;
verifying and programming said plurality of memory cells using incremental changes in a programming voltage, said verifying including verifying a memory cell is properly programmed within a margin,
wherein a valid voltage having a highest voltage and a valid voltage having a lowest voltage are verified relative to a first margin, other valid voltages are verified relative to a second margin, the first margin being greater than said second margin.