High-speed and low-power differential non-volatile content addressable memory cell and array
View Patent ↗A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
1. A differential non-volatile content addressable memory cell comprising:
a pair of non-volatile storage elements each of said storage elements is characterized by capable of being in one of two non-volatile states: a first state in which a first current flows through said storage element, and a second state in which a second current less than said first current flows through said storage element;
a match line;
a volatile storage element capable of storing said first state and said second state; said volatile storage element having a first output and a second output; said first and second outputs for controlling the flow of current from said match line; and
a pair of differential data lines; each for supplying data to one of said non-volatile storage elements, and for transferring the data from said pair of non-volatile storage elements to said volatile storage element; and for controlling the flow of current from said match line.
2. The differential non-volatile content addressable memory cell of claim 1 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said second terminal and said first terminal;
a floating gate disposed over a first portion of said channel and said second terminal and is insulated therefrom;
a control gate having a first section disposed over a second portion of said channel and insulated therefrom, and having a second section over said floating gate and is insulated therefrom; and
wherein said differential data line connects to said first terminal of each non-volatile storage element.
3. A differential non-volatile content addressable memory array comprising:
a plurality of cells arranged in a plurality of rows and columns; each cell comprising:
a pair of non-volatile storage elements each of said storage elements is characterized by capable of being in one of two non-volatile states: a first state in which a first current flows through said storage element, and a second state in which a second current less than said first current flows through said storage element;
a match line connecting cells arranged in the same row;
a volatile storage element capable of storing said first state and said second state; said volatile storage element having a first output and a second output; said first and second outputs for controlling the flow of current from said match line; and
a pair of differential data lines connecting cells in the same column, each data line for supplying data to one of said non-volatile storage elements, and for transferring the data from said pair of non-volatile storage elements to said volatile storage element; and for controlling the flow of current from said match line.
4. The differential non-volatile content addressable memory cell of claim 3 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said second terminal and said first terminal;
a floating gate disposed over a first portion of said channel and said second terminal and is insulated therefrom;
a control gate having a first section disposed over a second portion of said channel and insulated therefrom, and having a second section over said floating gate and is insulated therefrom; and
wherein said differential data line connects to said first terminal of each non-volatile storage element.
5. The memory cell of claim 1 wherein a single bit/compare line is used both for storing data into non-volatile memory and for comparing data on a compare line with data in the volatile storage element.
6. The memory cell of claim 1 wherein a compare data signal is used to control current flow in a channel.
7. The memory cell of claim 1 wherein a compare data line and compare data bar are not connected to a transistor channel, thereby reducing leakage current.
8. The memory cell of claim 6 wherein a compare data line and compare data bar are not connected to a transistor channel, thereby reducing leakage current.
9. The memory cell of claim 1 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said second terminal and said first terminal;
a floating gate disposed over a first portion of said channel and said second terminal and is insulated therefrom; and
a control gate having a first section disposed over a second portion of said channel and insulated therefrom, and having a second section over said floating gate and is insulated therefrom.
10. The memory cell of claim 9 wherein said second terminals of each of said storage elements in the same memory cell are connected together.
11. The memory cell of claim 1 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said first and second terminals;
a floating gate disposed over said channel and is insulated therefrom; and
a control gate disposed over said floating gate and is insulated therefrom.
12. The memory cell of claim 11 wherein said second terminals of each of said storage elements in the same memory cell are connected together.
13. The memory cell of claim 3 wherein a single bit/compare line is used both for storing data into non-volatile memory and for comparing data on a compare line with data in the volatile storage element.
14. The memory cell of claim 3 wherein a compare data signal is used to control current flow in a channel.
15. The memory cell of claim 3 wherein a compare data line and compare data bar are not connected to a transistor channel, thereby reducing leakage current.
16. The memory cell of claim 14 wherein a compare data line and compare data bar are not connected to a transistor channel, thereby reducing leakage current.
17. The memory cell of claim 3 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said second terminal and said first terminal;
a floating gate disposed over a first portion of said channel and said second terminal and is insulated therefrom; and
a control gate having a first section disposed over a second portion of said channel and insulated therefrom, and having a second section over said floating gate and is insulated therefrom.
18. The memory cell of claim 17 wherein said second terminals of each of said storage elements in the same memory cell are connected together.
19. The memory cell of claim 3 wherein each of said non-volatile storage elements comprises:
a first terminal in a semiconductor substrate;
a second terminal in said semiconductor substrate;
a channel between said first and second terminals;
a floating gate disposed over said channel and is insulated therefrom; and
a control gate disposed over said floating gate and is insulated therefrom.
20. The memory cell of claim 19 wherein said second terminals of each of said storage elements in the same memory cell are connected together.