Semiconductor memory array of floating gate memory cells with buried floating gate
View Patent ↗An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.
1. An electrically programmable and erasable memory device, comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
a pair of trenches formed into the substrate surface, wherein a strip of the substrate is disposed between the pair of trenches;
a first region of a second conductivity type formed in the substrate strip;
a pair of second regions of the second conductivity type formed in the substrate and spaced apart from the first region;
a pair of channel regions each extending from the first region to one of the second regions and each having a first portion extending underneath one of the trenches, a second portion not disposed in the substrate strip and extending along the one trench, and a third portion extending along the substrate surface;
a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the trenches; and
a pair of electrically conductive control gates each disposed over and insulated from one of the channel region third portions.
2. The device of claim 1 , wherein each of the floating gates is disposed adjacent to and insulated from the first and second portions of one of the channel regions for controlling a conductivity thereof.
3. The device of claim 1 , wherein each of the channel regions includes a fourth portion disposed in the substrate strip and extending along one of the trenches.
4. The device of claim 3 , wherein each of the floating gates is disposed adjacent to and insulated from the first, second and fourth portions of one of the channel regions for controlling a conductivity thereof.
5. The device of claim 3 , wherein the channel region first and third portions are generally parallel to the substrate surface, and the channel region second and fourth portions are generally perpendicular to the substrate surface.
6. The device of claim 3 , wherein the floating gates extend deeper into the substrate than does the first region.
7. The device of claim 3 , wherein:
each of the trenches includes opposing first and second sidewalls and a bottom wall;
the first region is disposed between the first sidewalls of the pair of trenches;
each of the channel region fourth portions is disposed along one of the first sidewalls;
each of the channel region first portions is disposed along one of the bottom walls; and
each of the channel region second portions is disposed along one of the second sidewalls.
8. The device of claim 3 , further comprising:
a second pair of trenches formed into the substrate surface, wherein a second strip of the substrate is disposed between the second pair of trenches, and wherein one of the second regions is formed in the second substrate strip;
one of the channel regions includes a fifth portion not disposed in the second substrate strip and extending along one of the second pair of trenches, a sixth portion extending underneath one of the second pair of trenches, and a seventh portion disposed in the second substrate strip and extending along one of the second pair of trenches; and
a second pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the second pair of trenches.
9. The device of claim 1 , wherein:
each of the trenches includes opposing first and second sidewalls and a bottom wall;
the first region is disposed between the first sidewalls of the pair of trenches;
each of the channel region first portions is disposed along one of the bottom walls; and
each of the channel region second portions is disposed along one of the second sidewalls.
10. The device of claim 1 , wherein each of the floating gates has an edge that faces one of the control gates and is insulated therefrom with insulation material having a thickness that permits tunneling of charges from the edge to the one control gate.
11. The device of claim 1 , wherein the first region is disposed laterally adjacent to and insulated from the floating gates.
12. The device of claim 1 , further comprising:
an electrically conductive erase gate that is insulated from the floating gates and the control gates, wherein each of the floating gates has an edge that faces the erase gate and is insulated therefrom with insulation material having a thickness that permits tunneling of charges from the edge to the erase gate.
13. The device of claim 1 , further comprising:
a second pair of trenches formed into the substrate surface, wherein a second strip of the substrate is disposed between the second pair of trenches, and wherein one of the second regions is formed in the second substrate strip;
one of the channel regions includes a fourth portion not disposed in the second substrate strip and extending along one of the second pair of trenches, and a fifth portion extending underneath one of the second pair of trenches; and
a second pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the second pair of trenches.
14. The device of claim 13 , wherein the control gates are integrally formed together from continuously formed conductive material.
15. An array of electrically programmable and erasable memory devices, comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
spaced apart isolation regions of the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and
each of the active regions including a plurality of pairs of memory cells, wherein each of the memory cell pairs comprises:
a pair of trenches formed into the substrate surface, wherein a strip of the substrate is disposed between the pair of trenches,
a first region of a second conductivity type formed in the substrate strip,
a pair of second regions of the second conductivity type formed in the substrate and spaced apart from the first region,
a pair of channel regions each extending from the first region to one of the second regions and each having a first portion extending underneath one of the trenches, a second portion not disposed in the substrate strip and extending along the one trench, and a third portion extending along the substrate surface,
a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the trenches, and
a pair of electrically conductive control gates each disposed over and insulated from one of the channel region third portions.
16. The array of claim 15 , wherein each of the floating gates is disposed adjacent to and insulated from the first and second portions of one of the channel regions for controlling a conductivity thereof.
17. The array of claim 15 , wherein each of the channel regions includes a fourth portion disposed in one of the substrate strips and extending along one of the trenches.
18. The array of claim 17 , wherein each of the floating gates is disposed adjacent to and insulated from the first, second and fourth portions of one of the channel regions for controlling a conductivity thereof.
19. The array of claim 17 , wherein the channel region first and third portions are generally parallel to the substrate surface, and the channel region second and fourth portions are generally perpendicular to the substrate surface.
20. The array of claim 17 , wherein the floating gates extend deeper into the substrate than do the first regions.
21. The array of claim 17 , wherein:
each of the trenches includes opposing first and second sidewalls and a bottom wall;
each of the first regions is disposed between the first sidewalls of one of the trench pairs;
each of the channel region fourth portions is disposed along one of the first sidewalls;
each of the channel region first portions is disposed along one of the bottom walls; and
each of the channel region second portions is disposed along one of the second sidewalls.
22. The array of claim 15 , wherein:
each of the trenches includes opposing first and second sidewalls and a bottom wall;
each of the first regions is disposed between the first sidewalls of one of the trench pairs;
each of the channel region first portions is disposed along one of the bottom walls; and
each of the channel region second portions is disposed along one of the second sidewalls.
23. The array of claim 15 , wherein each of the floating gates has an edge that faces one of the control gates and is insulated therefrom with insulation material having a thickness that permits tunneling of charges from the edge to the one control gate.
24. The array of claim 15 , wherein each of the first regions is disposed laterally adjacent to and insulated from one of the floating gate pairs.
25. The array of claim 15 , further comprising:
a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
26. The array of claim 15 , further comprising:
a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the first regions from each of the active regions.
27. The array of claim 15 , wherein each of the memory cell pairs further comprises:
an electrically conductive erase gate that is insulated from the pair of floating gates and the pair of control gates, wherein each of the floating gates has an edge that faces the erase gate and is insulated therefrom with insulation material having a thickness that permits tunneling of charges from the edge to the erase gate.
28. The array of claim 27 , further comprising:
a plurality of conductive erase lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the erase gates from each of the active regions.
29. An array of electrically programmable and erasable memory devices, comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
spaced apart isolation regions of the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and
each of the active regions including a plurality of pairs of memory cells, wherein each one of the memory cell pairs comprises:
a pair of trenches formed into the substrate surface, wherein a strip of the substrate is disposed between the pair of trenches,
a first region of a second conductivity type formed in the substrate strip,
a pair of channel regions each extending from the first region of the one pair of memory cells to first regions of adjacent pairs of memory cells, wherein each of the channel regions includes a first portion extending underneath one of the trenches, a second portion not disposed in the substrate strip and extending along the one trench, a third portion extending along the substrate surface, a fourth portion extending along one of the trenches for one of the adjacent pairs of memory cells and a fifth portion extending underneath the one trench from the one adjacent pair of memory cells,
a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the trenches, and
a pair of electrically conductive control gates each disposed over and insulated from one of the channel region third portions.
30. The array of claim 29 , wherein for each of the active regions, the control gates therein are integrally formed together from continuously formed conductive material.
31. The array of claim 29 , wherein each of the channel regions further includes:
a sixth portion disposed in the substrate strip for the one memory cell pair and extending along one of the trenches for the one memory cell pair; and
a seventh portion disposed in the substrate strip for the one adjacent pair of memory cells and extending along one of the trenches for the one adjacent pair of memory cells.
32. An electrically programmable and erasable memory device, comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
a first trench formed into the substrate surface;
a second trench formed into the substrate surface that is spaced apart from the first trench by a portion of the substrate;
a first region of a second conductivity type formed in the substrate adjacent the first trench and not in the substrate portion;
a second region of the second conductivity type formed in the substrate adjacent the second trench and not in the substrate portion;
a channel region of the substrate extending between the first and second regions, wherein the channel region includes a first portion extending from the first region and along the first trench, a second portion extending underneath the first trench, a third portion disposed in the substrate portion and extending along the first trench, a fourth portion disposed in the substrate portion and extending along the substrate surface, a fifth portion disposed in the substrate portion and extending along the second trench, a sixth portion extending underneath the second trench, and a seventh portion extending from the second region and along the second trench;
a pair of electrically conductive floating gates each having at least a lower portion thereof disposed in one of the first and second trenches; and
an electrically conductive control gate disposed over and insulated from the channel region fourth portion.
33. The device of claim 32 , wherein:
the first floating gate is disposed adjacent to and insulated from the first, second and third portions of the channel region for controlling a conductivity thereof; and
the second floating gate is disposed adjacent to and insulated from the fifth, sixth and seventh portions of the channel region for controlling a conductivity thereof.
34. The device of claim 32 , wherein the channel region first, third, fifth and seventh portions are generally perpendicular to the substrate surface, and the channel region second, fourth and sixth portions are generally parallel to the substrate surface.
35. The device of claim 32 , wherein the floating gates extend deeper into the substrate than do the first and second regions.
36. The device of claim 32 , further comprising:
a pair of conductive erase gates that are insulated from the floating gates and the control gate, wherein each of the floating gates has an edge that faces one of the erase gates and is insulated therefrom with insulation material having a thickness that permits tunneling of charges from the edge to the erase gate.