Method of testing an integrated circuit die, and an integrated circuit die
View Patent ↗In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.
1. A method of testing an unpackaged integrated circuit die, having a plurality of first input/output pads, said method comprising:
selecting a second plurality of input/output pads, wherein said second plurality being less than the first plurality;
fabricating in said die a serial electrical connection between all of the input/output pads of said die which are not of the second plurality (hereinafter: “third plurality”); wherein said third plurality having a first end and a second end;
connecting the first end of the third plurality to one of the input/output pads of said second plurality and the second end of the third plurality to another of the input/output pads of said second plurality; and
testing the second plurality of input/output pads.
2. The method of claim 1 wherein the fabricating step comprises:
forming an input buffer, having an input and an output, and an output buffer, having an input and an output, for each of the pads of the third plurality, with each pad connected to the input of the input buffer, and to the output of the output buffer; and
electrically connecting the output of an input buffer of one pad of the third plurality to the input of an output buffer of an adjacent pad of the third plurality.
3. The method of claim 2 wherein the second plurality is along the periphery of said integrated circuit die.
4. The method of claim 3 wherein said die is substantially rectilinearly shaped, and wherein said second plurality is along opposite sides of the periphery of said die.
5. A method of testing an integrated circuit device, having an integrated circuit die with a plurality of first input/output pads, said method comprising:
selecting a second plurality of input/output pads, wherein said second plurality being less than the first plurality;
fabricating in said die a serial electrical connection between all of the input/output pads of said die which are not of the second plurality (hereinafter: “third plurality”); wherein said third plurality having a first end and a second end;
connecting the first end of the third plurality to one of the input/output pads of said second plurality and the second end of the third plurality to another of the input/output pads of said second plurality;
testing the second plurality of input/output pads;
packaging said die into the integrated device; and
testing the device by testing said third plurality of input/output pads.