Granted Patent B2

US 7,831,872 · App. 12/637,365 · Granted Nov 9, 2010

Abstract

Claims (8)

1. A test circuit comprising:

a first node for coupling to a digital multilevel memory system;

a first switch coupled to the first node to selectively couple an input node to the first node in response to a first signal indicative of a write mode of the digital multilevel memory system;

a transistor including first and second terminals spaced apart with a channel between the first and the second terminals and including a gate controlling current in said channel, said first terminal being coupled to a voltage node, the second terminal being coupled to an output node;

a second switch selectively coupling the first node to the gate of the transistor in response to a second signal indicative of a read mode of the digital multilevel memory system.

2. The test circuit of claim 1 further comprising a load circuit coupled to the output node.

3. The test circuit of claim 1 wherein the first and second switches comprise second and third transistors, respectively.

4. The test circuit of claim 1 wherein the digital multilevel memory system includes non-volatile memory.

Assignments (14)