Flash memory system with EEPROM functionality
View Patent ↗The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.
1. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a word line select line for controlling access by a word line to the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
2. The device of claim 1 , further comprising: a word line deselect line for preventing access by a word line to the byte of memory cells.
3. The device of claim 2 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
4. The device of claim 3 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
5. The device of claim 1 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
6. The device of claim 5 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
7. The device of claim 1 , further comprising: a word line deselect transistor for preventing access by a word line to the byte of memory cells.
8. The device of claim 1 , wherein within the byte, a number of cells less than the number of cells in the byte can be read or programmed.
9. The device of claim 8 , wherein the read or program is done until all cells within the byte is completed.
10. The device of claim 1 , further comprising complementary bitline and bitline bar for a unit cell pair sharing same source line.
11. The device of claim 10 , wherein the complementary bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation.
12. The device of claim 1 , wherein a bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation.
13. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a first source line select line for controlling access by a first source line to the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
14. The device of claim 13 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
15. The device of claim 13 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
16. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a word line select transistor for controlling access by a word line to the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
17. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a first source line select transistor for controlling access by a first source line to the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
18. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
wherein each column of memory cells is coupled to two bit lines; and
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
19. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same time;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
20. The device of claim 19 , further comprising an enable source line select read line for enabling the use of the source line select read line.
21. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a word line for accessing two rows of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
22. The device of claim 21 , further comprising a word line select line for enabling the word line.
23. The device of claim 21 , further comprising a transistor for enabling the word line.
24. The device of claim 21 , further comprising a transistor for enabling the programming of two pairs of bytes of memory cells.
25. The device of claim 21 , further comprising a transistor for enabling the reading of two pairs of bytes of memory cells.
26. The device of claim 21 , further comprising a transistor for enabling the programming of a pair of bytes of memory cells.
27. The device of claim 21 , further comprising a transistor for enabling the reading of a pair of bytes of memory cells.
28. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
wherein half of the rows of memory cells are not used during operation of the device; and
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
29. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same times;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
30. The device of claim 29 , further comprising an enable source line select read line for enabling the use of the source line select read line.
31. The device of claim 29 , further comprising a transistor for de-selecting an internal memory cell word line, such that memory cells in a first row can be selected and memory cells in a second row sharing a source line with the first row can be de-selected.
32. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a control gate select line for controlling access by a word line to the control gate of each memory cell in the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
33. The device of claim 32 , further comprising: a word line select line for controlling access by a word line to the byte of memory cells.
34. The device of claim 33 , further comprising: a word line deselect line for preventing access by a word line to the byte of memory cells.
35. The device of claim 32 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
36. The device of claim 33 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
37. The device of claim 34 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
38. The device of claim 35 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
39. The device of claim 36 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
40. The device of claim 37 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
41. The device of claim 32 , further comprising: a word line select transistor for controlling access by a word line to the byte of memory cells.
42. The device of claim 41 , further comprising: a word line deselect transistor for preventing access by a word line to the byte of memory cells.
43. The device of claim 32 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
44. The device of claim 41 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
45. The device of claim 42 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
46. The device of claim 43 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
47. The device of claim 44 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
48. The device of claim 45 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
49. The device of claim 32 , further comprising two bytes sharing one source line.
50. The device of claim 49 , wherein an unselected byte is inhibited by an inhibit CG voltage in programming.
51. The device of claim 33 , wherein within the byte, a number of cells less than the number of cells in the byte can be read or programmed.
52. The device of claim 51 , wherein the read or program is done until all cells within the byte is completed.
53. The device of claim 33 , further comprising complementary bitline and bitline bar for a unit cell pair sharing same source line.
54. The device of claim 53 , wherein the complementary bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation.
55. The device of claim 33 , wherein the word lines for the half of the rows are connected to ground bias.
56. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
wherein a bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation; and
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
57. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line;
wherein a bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation; and
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
58. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a source line select read line coupled to a pair of bytes of memory cells that enable the reading of both bytes at the same time;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
59. The device of claim 58 , further comprising an enable source line select read line for enabling the use of the source line select read line.
60. A non-volatile memory device comprising:
an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a control gate for connecting to a control gate line, an erase gate for connecting to an erase gate line, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; and
a control gate select line for controlling access by a word line to the control gate of each memory cell in the byte of memory cells;
wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.
61. The device of claim 60 , further comprising: an erase gate select line for controlling access by a word line to the erase gate of each memory cell in the byte of memory cells.
62. The device of claim 61 , further comprising: a word line select line for controlling access by a word line to the byte of memory cells.
63. The device of claim 62 , further comprising: a word line deselect line for preventing access by a word line to the byte of memory cells.
64. The device of claim 61 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
65. The device of claim 62 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
66. The device of claim 63 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.
67. The device of claim 64 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
68. The device of claim 65 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
69. The device of claim 66 , further comprising: a second source line select line for controlling access by a second source line to the byte of memory cells, the first source line select line being used for read operations and the second source line select line being used for program operations.
70. The device of claim 60 , further comprising: an erase gate select transistor for controlling access by a word line to the erase gate of each memory cell in the byte of memory cells.
71. The device of claim 70 , further comprising: a word line select transistor for controlling access by a word line to the byte of memory cells.
72. The device of claim 71 , further comprising: a word line deselect transistor for preventing access by a word line to the byte of memory cells.
73. The device of claim 70 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
74. The device of claim 71 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
75. The device of claim 72 , further comprising: a first source line select transistor for controlling access by a first source line to the byte of memory cells.
76. The device of claim 73 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
77. The device of claim 74 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
78. The device of claim 75 , further comprising: a second source line select transistor for controlling access by a second source line to the byte of memory cells, the first source line select transistor being used for read operations and the second source line select transistor being used for program operations.
79. The device of claim 60 , further comprising two bytes sharing one source line.
80. The device of claim 79 , wherein the unselected byte is inhibited by an inhibit CG voltage during programming.
81. The device of claim 62 , wherein within the byte, a number of cells less than the number of cells in the byte can be read or programmed.
82. The device of claim 81 , wherein the read or program is done until all cells within the byte is completed.
83. The device of claim 62 , further comprising complementary bitline and bitline bar for a unit cell pair sharing same source line.
84. The device of claim 82 , wherein the complementary bitline is used to pull down the source line to a low voltage for the selected bitline during a read operation.