Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation
View Patent ↗Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
1. A differential amplifier comprising:
an output transconductance amplifier comprising:
a first PMOS transistor including first and second terminals spaced apart with a channel therebetween and including a gate for controlling current in said channel, said first terminal being coupled to a first voltage terminal, said gate being coupled to receive a bias voltage;
a second PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said gate being coupled to a first input terminal, said first terminal being coupled to the second terminal of the first PMOS transistor, said bulk voltage terminal being coupled to a second voltage terminal to receive a voltage different than the voltage on the first voltage terminal;
a first NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to a ground terminal, said gate being coupled to said first terminal of the first NMOS transistor and said second terminal of said second PMOS transistor;
a third PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said second terminal being coupled to a first output terminal, said gate being coupled to a second input terminal, said first terminal being coupled to the second terminal of the first PMOS transistor, said bulk voltage terminal being coupled to the second voltage terminal;
a second NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to the ground terminal, said gate being coupled to the first terminal of the first NMOS transistor, said first terminal of the second NMOS transistor being coupled to the first output terminal;
an output stage coupled to the first output terminal, wherein said output stage comprising:
a fourth PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal, said second terminal being coupled to said gate, said first terminal being coupled to the first voltage terminal;
a third NMOS transistor including first and second terminals spaced apart with a channel therebetween, and including a gate for controlling current in said channel, said second terminal being coupled to the ground terminal, said gate being coupled to the second terminal of the second PMOS transistor, said first terminal being coupled to the second terminal of the fourth PMOS transistor;
a fifth PMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal to receive a first adjustable voltage, said second terminal being coupled to a second output terminal, said gate being coupled to the second terminal of the fourth PMOS transistor, said first terminal being coupled to the first voltage terminal; and
a fourth NMOS transistor including first and second terminals spaced apart with a channel therebetween, including a gate for controlling current in said channel, and including a bulk voltage terminal to receive a second adjustable voltage, said second terminal being coupled to the ground terminal, said gate being coupled to the second terminal of the second PMOS transistor, said first terminal being coupled to the second terminal of the fifth PMOS transistor; and
a bulk voltage generator coupled to at least one of said PMOS or NMOS transistors to generate a bulk voltage different than a supply voltage of the output transconductance amplifier.
2. The differential amplifier of claim 1 wherein the size of any of the fourth PMOS transistor, third NMOS transistor, fifth PMOS transistor or fourth NMOS transistor of the output stage can be trimmed.
3. The differential amplifier of claim 1 wherein the bulk voltage generator further comprises:
a current source, having a first terminal and a second terminal;
a plurality of resistors, each resistor having a first terminal and a second terminal;
said plurality of resistors and said current source are connected in series, and connected between a voltage node and ground; and
a plurality of switches, each switch for selectively connecting one of said plurality of resistors to an output node for supplying the bulk voltage.