Three-dimensional flash memory system
A three-dimensional flash memory system is disclosed.
1. An memory apparatus, comprising:
a first die comprising a first array of flash memory cells;
a first control circuit for generating sectors of a first size with the first array;
a second die comprising a second array of flash memory cells;
a second control circuit for generating sectors of a second size within the second array;
a third die comprising redundancy circuitry for the first die and the second die;
a plurality of TSV connections between the first die and third die; and
a plurality of TSV connections between the second die and third die.
2. The apparatus of claim 1 , wherein the first size is eight bytes.
3. The apparatus of claim 1 , wherein the first size is four Kbytes.
4. The apparatus of claim 1 , wherein the redundancy circuitry comprises a storage device for storing a map of defective cells in the first array, wherein each defective cell is associated with a working cell.
5. The apparatus of claim 4 , wherein the storage device stores a map of defective cells in the second array, wherein each defective cell is associated with a working cell.
6. The apparatus of claim 5 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
7. The apparatus of claim 4 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
8. The apparatus of claim 1 , wherein the first die comprises a third array of flash memory cells.
9. The apparatus of claim 1 , wherein the third die further comprises a powerup recall controller used for the first die and second die.
10. A memory apparatus, comprising:
a first die comprising a first array of flash memory cells;
a second die comprising a second array of flash memory cells;
a redundant array shared between the first die and second die;
redundancy circuitry comprising a storage device for storing a map of defective cells in one or both of the first array and the second array, wherein each defective cell is associated with a working cell in the redundant array; and
a plurality of TSV connections between the first die and second die.
11. The apparatus of claim 10 , wherein an TO width of the memory apparatus is configurable by combining the first die and second die.
12. The apparatus of claim 11 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
13. The apparatus of claim 10 , wherein the first die is configured to use the redundant array.
14. The apparatus of claim 13 , wherein the second die is configured to use the redundant array.
15. The apparatus of claim 14 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
16. The apparatus of claim 13 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
17. The apparatus of claim 10 , wherein the map identifies defective cells in the first array.
18. The apparatus of claim 17 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
19. The apparatus of claim 10 , wherein the map identifies defective cells in the second array.
20. The apparatus of claim 19 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.
21. The apparatus of claim 10 , wherein the redundancy circuitry further comprises a redundancy comparator that compares an incoming address with addresses of defective cells stored in the storage device.