Three-dimensional flash memory system
View Patent ↗A three-dimensional flash memory system is disclosed.
1. A memory apparatus, comprising:
a first die comprising a first array of flash memory cells;
a first control circuit for generating sectors of a first size with the first array;
a second die comprising a second array of flash memory cells;
a second control circuit for generating sectors of a second size different than the first size within the second array; and
a plurality of TSV connections between the first die and second die.
2. The apparatus of claim 1 , wherein the first die comprises sensing circuitry.
3. The apparatus of claim 1 , wherein the first die comprises a first charge pump.
4. The apparatus of claim 3 , wherein the second die is configured to use the first charge pump in reading data from the second array.
5. The apparatus of claim 1 , wherein the first die comprises control logic.
6. The apparatus of claim 5 , wherein the second die is configured to use the control logic.
7. The apparatus of claim 1 , wherein the first size is eight bytes.
8. The apparatus of claim 1 , wherein the first size is four Kbytes.
9. The apparatus of claim 1 , wherein at least one of the sectors of a first size comprise multiple word lines, one erase gate, one source line, and one control gate.
10. The apparatus of claim 9 , wherein at least two of the sectors of a first size share the same word line.
11. The apparatus of claim 9 , wherein at least two of the sectors of a first size use different erase gates, different control gates, and different source lines.
12. The apparatus of claim 1 , wherein at least one of the sectors of a first size emulates an EEPROM sector.
13. The apparatus of claim 12 , wherein the at least one of the sectors of a first size that emulates an EEPROM sector comprises a plurality of word lines, one erase gate, one source line, and one control gate.
14. The apparatus of claim 12 , wherein at least two of the sectors of a first size that emulate an EEPROM sector share the same word line.
15. The apparatus of claim 12 , wherein at least two of the sectors of a first size that emulate an EEPROM sector use different erase gates, different control gates, and different source lines.
16. An memory apparatus, comprising:
a first die comprising a first array of flash memory cells;
a first control circuit for emulating an EEPROM with sectors of a first size using the first array;
a second die comprising a second array of flash memory cells;
a second control circuit for generating sectors of a second size different than the first size within the second array; and
a plurality of TSV connections between the first die and second die.
17. The apparatus of claim 16 , wherein the first die comprises sensing circuitry.
18. The apparatus of claim 16 , wherein the first die comprises a first charge pump.
19. The apparatus of claim 18 , wherein the second die is configured to use the first charge pump in operating on data from the second array.
20. The apparatus of claim 16 , wherein the first die comprises control logic.
21. The apparatus of claim 20 , wherein the second die is configured to use the control logic.
22. The apparatus of claim 16 , wherein the first die further comprises a buffer TSV circuit.
23. The apparatus of claim 16 , wherein the first die further comprises a test pad.
24. The apparatus of claim 16 , wherein the first die further comprises a sense circuit and a TSV is coupled to the source of a sensing cascoding device.
25. The apparatus of claim 16 , wherein the plurality of TSV connections comprise a plurality of shielded TSV connections.
26. A memory apparatus, comprising:
a first die comprising a first array of flash memory cells created by a first semiconductor process;
a second die comprising a second array of flash memory cells created by a second semiconductor process different than the first semiconductor process;
a plurality of TSV connections between the first die and second die.
27. The apparatus of claim 26 , wherein the first die comprises sensing circuitry.
28. The apparatus of claim 26 , wherein the first die comprises a first charge pump.
29. The apparatus of claim 28 , wherein the second die is configured to use the first charge pump in reading data from the second array.
30. The apparatus of claim 26 , wherein the first die comprises control logic.
31. The apparatus of claim 30 , wherein the second die is configured to use the control logic.
32. The apparatus of claim 26 , wherein the first semiconductor process is 32 nm.
33. The apparatus of claim 26 , wherein the first semiconductor process is 22 nm.
34. A memory apparatus, comprising:
a first die comprising a first array of flash memory;
a second die comprising a second array of flash memory cells;
a force-sense high voltage supply system for first and second dies; and
a plurality of TSV connections between the first die and second die.
35. The apparatus of claim 34 , wherein IO widths are configurable by combining first and second dies.
36. The apparatus of claim 34 , wherein the TSV connection integrity are testable by TSV self test engine on the first die.
37. The apparatus of claim 34 , wherein the force-sense scheme applying to source line current bias terminal of flash memory cell.
38. A memory apparatus, comprising:
a first die comprising a first array of flash memory cells;
a second die comprising a second array of flash memory cells;
a sensing circuit shared between the first die and second die;
a plurality of TSV connections between the first die and second die.
39. The apparatus of claim 38 , wherein an IO width of the memory apparatus is configurable by combining the first die and second die.
40. The apparatus of claim 39 , wherein the second die is configured to use the sensing circuit.