Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio
View Patent ↗A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
1. In a flash memory cell of the type having a substrate of a first conductivity type, a plurality of stacked pairs of floating gates and control gates with the floating gate positioned over a portion of the substrate and insulated therefrom, and the control gate over the floating gate and insulated therefrom; a plurality of erase gates over the substrate and insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate, wherein a method of erasing the flash memory cell comprising:
applying a pulse of a first positive voltage to alternating erase gates (“first alternating gates”); and
applying a negative voltage to erase gates other than the first alternating gates (“second alternating gates”).
2. The method of claim 1 further comprising:
applying the negative voltage to the control gates.
3. The method of claim 1 further comprising:
applying a pulse of the first positive voltage for a preset number of times before performing an erase verify operation.
4. The method of claim 1 further comprising:
applying the negative voltage to the first alternating gates;
applying a pulse of the first positive voltage to the second alternating gates.
5. The method of claim 2 further comprising:
performing an erase verify operation;
terminating the erase method in the event the erase verify operation shows the memory cells is erased;
continuing the erase operation in the event the memory cell is not completely erased, by applying a pulse of a second positive voltage to the first alternating gates.
6. The method of claim 5 wherein the second positive voltage is greater than the first positive voltage.
7. The method of claim 1 wherein said memory cell is of NAND type.
8. The method claim 1 wherein said memory cell is of NOR type.