Power sequencing for embedded flash memory devices
View Patent ↗A system and method for improved power sequencing within an embedded flash memory device is disclosed.
1. A power management unit comprising a first voltage source, a second voltage source, and a third voltage source configured to perform a power-on sequence, wherein:
during a first time period, the voltage output from the first voltage source ramps upward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during a second time period immediately following the first time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during a third time period immediately following the second time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source ramps upward, and the voltage output from the third voltage source remains at a constant level;
during a fourth time period immediately following the third time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and
during a fifth time period immediately following the fourth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps upward.
2. The power management unit of claim 1 , wherein the first voltage source, the second voltage source, and the third voltage source are configured to perform a power-down sequence, wherein:
during a sixth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps downward;
during a seventh time period immediately following the sixth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during an eighth time period immediately following the seventh time period, the voltage output from the first voltage source ramps downward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and
during a ninth time period immediately following the eighth time period, the voltage output from the first voltage source ramps downward, the voltage output from the second voltage source ramps downward, and the voltage output from the third voltage source remains at a constant level.
3. A method of performing a power-on sequence using a first voltage source, a second voltage source, and a third voltage source, the method comprising:
during a first time period, the voltage output from the first voltage source ramps upward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during a second time period immediately following the first time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during a third time period immediately following the second time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source ramps upward, and the voltage output from the third voltage source remains at a constant level;
during a fourth time period immediately following the third time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and
during a fifth time period immediately following the fourth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps upward.
4. The method of claim 3 , further comprising a power-down sequence comprising:
during a sixth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source ramps downward;
during a seventh time period immediately following the sixth time period, the voltage output from the first voltage source remains at a constant level, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level;
during an eighth time period immediately following the seventh time period, the voltage output from the first voltage source ramps downward, the voltage output from the second voltage source remains at a constant level, and the voltage output from the third voltage source remains at a constant level; and
during a ninth time period immediately following the eighth time period, the voltage output from the first voltage source ramps downward, the voltage output from the second voltage source ramps downward, and the voltage output from the third voltage source remains at a constant level.