Method of forming a self-aligned stack gate structure for use in a non-volatile memory array
View Patent ↗A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.
1. A method forming a plurality of connected stack gate structure for use in a non-volatile memory array, said method comprising:
forming a stack gate structure by:
forming a first insulating layer on a semiconductor substrate;
forming a charge holding layer on said first insulating layer;
forming a second insulating layer over the charge holding layer;
forming a first polysilicon layer over the second insulating layer, with said first polysilicon layer having a first top surface;
forming a third insulating layer with a third insulating material over the first top surface of the first polysilicon layer;
forming a first sacrificial layer over the third insulating layer, with said first sacrificial layer having a second top surface;
etching said stack gate structure in a plurality of spaced apart substantially parallel regions, from the second top surface downward into the semiconductor substrate, with each region extending in a first direction;
filling the etched spaced apart regions with the third insulating material, thereby forming isolation regions between adjacent active regions in the semiconductor substrate; and between adjacent stack gate structures;
planarizing said third insulating material such that the top surface of the third insulating material over the etched spaced apart regions is substantially co-planar with the second top surface;
removing the first sacrificial layer;
etching said third insulating material such that the first top surface of the first polysilicon layer is substantially cleared of any third insulating material;
forming a second polysilicon layer over the first polysilicon layer and over the third insulating material over the etched spaced apart regions, connecting the plurality of spaced apart stack gate structures;
forming a fourth insulating material over the second polysilicon layer; and
etching the resultant structure in a second direction substantially perpendicular to the first direction.
2. The method of claim 1 wherein said first insulating material and said third insulating material are the same.
3. The method of claim 2 wherein said third insulating material is silicon dioxide.
4. The method of claim 1 wherein said first sacrificial layer is silicon nitride.
5. The method of claim 1 wherein said charge holding layer is polysilicon.
6. The method of claim 1 wherein said charge holding layer is a charge trapping layer.
7. The method of claim 1 wherein said step of planarizing said third insulating material is a CMP process.
8. The method of claim 1 wherein said step of etching said third insulating layer etches the third insulating material between stack gate structures to be substantially co-planar with the top surface of the first polysilicon layer.
9. The method of claim 1 wherein said step of etching said third insulating layer etches the third insulating material between stack gate structures to be above the top surface of the first polysilicon layer.