Source synchronous CDMA bus interface
View Patent ↗A wireless IC interconnect system and a source synchronous CDMA (SS-CDMA) bus interface facilitate interconnections between first and second IC locations. A signal conveyed using the wireless system is modulated and capacitively coupled to a transmission medium, and then capacitively coupled from the medium to a receiver which demodulates the modulated signal and provides the demodulated signal to the second IC location. Multiple signals can be conveyed simultaneously by modulating and demodulating them using multiple access algorithms such as CDMA and/or FDMA. The SS-CDMA bus interface utilizes source synchronous signaling and CDMA techniques to provide high bus concurrency and low channel latency. The interface is re-configurable, and provides multi-chip access in high-bandwidth multi-drop parallel interconnection applications. The interface employs spread spectrum multiple access schemes, which enable two or more data bits to be sent through the same channel simultaneously and successfully recovered at the receiver.
1. A source synchronous CDMA bus interface, comprising:
a single data channel;
at least one data transmitter circuit coupled to said data channel at a first point;
at least one data receiver circuit coupled to said data channel at a second point;
a system clock line which runs adjacent and parallel to said data channel; and
a system clock signal applied to said system clock line such that said system clock signal propagates in parallel with data sent from said at least one data transmitter circuit to said at least one data receiver circuit via said data channel;
the at least one of said data transmitter circuits comprising:
a first clock signal generating circuit coupled at its input to said system clock line at a point approximately adjacent to said first point, said first clock generating circuit arranged to generate a first clock signal derived from said system clock signal;
a modulating circuit connected to receive base-band data to be transmitted via said data channel at a first input and a unique orthogonal code at a second input and to produce data modulated by said unique orthogonal code at an output; and
a transmitter connected to receive said modulated data and said first clock at respective inputs and which is arranged to use said first clock to align said modulated data with said system clock signal and to provide said aligned modulated data at an output which is coupled to said data channel at said first point such that said aligned modulated data is transmitted using source synchronous clocking;
the at least one of said data receiver circuits comprising:
a second clock signal generating circuit coupled at its input to said system clock line at a point approximately adjacent to said second point, said second clock generating circuit arranged to generate a second clock signal derived from said system clock signal;
a receiver coupled to said data channel at said second point such that it receives said aligned modulated data and said second clock at respective inputs and which is arranged to use said second clock to align said received data with said system clock signal; and
a demodulating circuit connected to receive said aligned received data at a first input and said unique orthogonal code at a second input and to produce data demodulated with said orthogonal code at an output and thereby recover said base-band data;
wherein said at least one data transmitter circuit and at least one data receiver circuit comprise two data transmitter circuits and two data receiver circuits, each of said modulating circuits receiving respective unique orthogonal codes and each of said demodulating circuits corresponding to one of said modulating circuits and receiving said modulating circuit's orthogonal code, said unique orthogonal codes enabling the aligned modulated data from said two data transmitter circuits to be conveyed via said single data channel to said two data receiving circuits simultaneously using 3-PAM signaling, said receiver comprising first and second 2-bit interleaving analog-to-digital converters (ADCs) for handling even and odd data, respectively, each of said 2-bit ADCs receiving two DC reference voltages such that said ADC converts said 3-PAM signal to thermometer coded data.
2. The bus interface of claim 1 , wherein said first and second clock generating circuits are delay-locked-loop (DLL) circuits.
3. The bus interface of claim 1 , wherein said first and second clock generating circuits are phase-locked-loop (PLL) circuits.
4. The bus interface of claim 1 , wherein said orthogonal codes are Walsh codes.
5. The bus interface of claim 1 , wherein said two data transmitter circuits share said first clock signal and the outputs of said two data transmitter circuits are connected together at a common node which is coupled to said data channel at said first point.
6. The bus interface of claim 1 , wherein the outputs of said two data transmitter circuits are coupled to said data channel at different points along said data channel, each of said data transmitter circuits having respective first clock circuits, the input of each first clock circuit connected to said system clock line at a point approximately adjacent to where said first clock circuit's data transmitter circuit is coupled to said data channel, such that the outputs of said data transmitter circuits are transmitted using source synchronous clocking and superposed in said data channel.
7. The bus interface of claim 1 , wherein said two data receiver circuits share said second clock signal and the inputs of said two data receiver circuits are connected together at a common node which is coupled to said data channel at said second point.
8. The bus interface of claim 1 , wherein the inputs of said two data receiver circuits are coupled to said data channel at different points along said data channel, each of said data receiver circuits having respective second clock circuits, the input of each second clock circuit connected to said system clock line at a point approximately adjacent to where said second clock circuit's data receiver circuit is coupled to said data channel.
9. The bus interface of claim 1 , further comprising a system controller which provides said unique orthogonal codes to said data transmitter circuits and said data receiving circuits such that aligned modulated data coupled to said data channel is received and demodulated by a specific data receiver circuit, said system controller thereby configuring said bus interface.
10. The bus interface of claim 1 , wherein said orthogonal codes are 2-bit Walsh codes.
11. The bus interface of claim 1 , wherein said orthogonal codes are 4-bit Walsh codes.
12. The bus interface of claim 1 , wherein said data channel is parallel terminated at each end.
13. The bus interface of claim 1 , wherein said data channel is a transmission line.
14. The bus interface of claim 1 , further comprising at least one data storage device interfaced to said two data transmitter circuits such that said bus interface provides a memory bus which conveys data from said at least one data storage device to said two data receiver circuits.
15. The bus interface of claim 14 , further comprising at least one CPU interfaced to said two data receiver circuits such that said memory bus conveys data from said at least one data storage device to said at least one CPU.
16. The bus interface of claim 14 , further comprising at least one memory controller interfaced to said two data receiver circuits such that said memory bus conveys data from said at least one data storage device to said at least one memory controller.
17. The bus interface of claim 1 , wherein said modulating circuit comprises at least one exclusive-OR gate connected to receive said base-band data and said unique orthogonal code at respective inputs and to produce said modulated data at said output, said modulated data cd 0 (t) given by:
cd 0 (t)=D 0 (t)⊕C 0 (t),
wherein D 0 (t) is said base-band data and C 0 (t) is said unique orthogonal code.
18. The bus interface of claim 1 , wherein each of said transmitters comprise an output driver having a current-mode open-drain structure.
19. The bus interface of claim 1 , wherein said demodulating circuit comprises a plurality of exclusive-OR gates connected to receive said even and odd thermometer coded data and said unique orthogonal codes and to de-spread said thermometer coded data using said unique orthogonal codes.
20. The bus interface of claim 19 , wherein said demodulating circuit further comprises a plurality of integrator circuits connected to receive said de-spread even and odd thermometer coded data and to integrate said data.
21. The bus interface of claim 20 , wherein said demodulating circuit further comprises a plurality of sense amplifier flip-flops (SAFF) connected to receive, amplify, and latch said integrated data and to recover said base-band data.
22. A source synchronous CDMA bus interface, comprising:
a single data channel;
at least one data transmitter circuit coupled to said data channel at a first point;
at least one data receiver circuit coupled to said data channel at a second point;
a system clock line which runs adjacent and parallel to said data channel; and
a system clock signal applied to said system clock line such that said system clock signal propagates in parallel with data sent from said at least one data transmitter circuit to said at least one data receiver circuit via said data channel;
the at least one of said data transmitter circuits comprising:
a first clock signal generating circuit coupled at its input to said system clock line at a point approximately adjacent to said first point, said first clock generating circuit arranged to generate a first clock signal derived from said system clock signal;
a modulating circuit connected to receive base-band data to be transmitted via said data channel at a first input and a unique orthogonal code at a second input and to produce data modulated by said unique orthogonal code at an output; and
a transmitter connected to receive said modulated data and said first clock at respective inputs and which is arranged to use said first clock to align said modulated data with said system clock signal and to provide said aligned modulated data at an output which is coupled to said data channel at said first point such that said aligned modulated data is transmitted using source synchronous clocking;
the at least one of said data receiver circuits comprising:
a second clock signal generating circuit coupled at its input to said system clock line at a point approximately adjacent to said second point, said second clock generating circuit arranged to generate a second clock signal derived from said system clock signal;
a receiver coupled to said data channel at said second point such that it receives said aligned modulated data and said second clock at respective inputs and which is arranged to use said second clock to align said received data with said system clock signal; and
a demodulating circuit connected to receive said aligned received data at a first input and said unique orthogonal code at a second input and to produce data demodulated with said orthogonal code at an output and thereby recover said base-band data;
wherein said system clock line runs adjacent and parallel to said data channel in a first direction, reverses direction and continues adjacent and parallel to said data channel in a second direction opposite said first direction, said system clock signal applied to said system clock line such that said system clock signal propagates down said system clock line in said first direction and continues down said system clock line is said second direction.
23. The bus interface of claim 22 , wherein said data channel conveys data bi-directionally between said data transmitter circuits and said data receiver circuits, a data transmitter circuit conveying data to a data receiver circuit in said first direction having their respective clock generating circuit inputs connected to respective points on the portion of said system clock line running in said first direction, and a data transmitter circuit conveying data to a data receiver circuit in said second direction having their respective clock generating circuit inputs connected to respective points on the portion of said system clock line running in said second direction.