Non-volatile memory array with concurrently formed low and high voltage logic devices
View Patent ↗A memory cell includes source and drain regions in a substrate with a channel region therebetween, an erase gate over the source region, a floating gate over a first channel region portion, a control gate over the floating gate, and a wordline gate over a second channel region portion. A first logic device includes second source and drain regions in the substrate with a second channel region therebetween under a first logic gate. A second logic device includes third source and drain regions in the substrate with a third channel region therebetween under a second logic gate. The wordline gate and the first and second logic gates comprise the same conductive metal material. The second logic gate is insulated from the third channel region by first and second insulation. The first logic gate is insulated from the second channel region by the second insulation and not by the first insulation.
1. A method of forming a semiconductor device, comprising:
forming a memory cell on a substrate by:
forming a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
forming a conductive erase gate over and insulated from the first source region,
forming a conductive floating gate over and insulated from a first portion of the first channel region,
forming a conductive control gate over and insulated from the conductive floating gate, and
forming a conductive word line gate over and insulated from a second portion of the first channel region;
forming a first logic device on the substrate by:
forming a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region, and
forming a conductive first logic gate over and insulated from the second channel region;
forming a second logic device on the substrate by:
forming a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region, and
forming a conductive second logic gate over and insulated from the third channel region;
wherein the forming of the conductive word line gate, the forming of the conductive first logic gate, and the forming of the conductive second logic gate comprise forming a conductive metal material over the substrate;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation formed over the substrate and by a second insulation formed over the substrate;
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the conductive erase gate is insulated from the first source region by the first insulation and by a third insulation, and not by the second insulation;
wherein the conductive floating gate is insulated from the first portion of the first channel region by the first insulation and not by the second insulation and not by the third insulation; and
wherein the conductive word line gate is insulated from the second portion of the first channel region by the first insulation and by the second insulation and not by the third insulation; and wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
2. A method of forming a semiconductor device, comprising:
forming a memory cell on a substrate by:
forming a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
forming a conductive erase gate over and insulated from the first source region,
forming a conductive floating gate over and insulated from a first portion of the first channel region,
forming a conductive control gate over and insulated from the conductive floating gate, and
forming a conductive word line gate over and insulated from a second portion of the first channel region;
forming a first logic device on the substrate by:
forming a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region, and
forming a conductive first logic gate over and insulated from the second channel region;
forming a second logic device on the substrate by:
forming a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region, and
forming a conductive second logic gate over and insulated from the third channel region;
wherein the forming of the conductive word line gate, the forming of the conductive first logic gate, and the forming of the conductive second logic gate comprise forming a conductive metal material over the substrate;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation formed over the substrate and by a second insulation formed over the substrate;
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the forming of the conductive erase gate comprises the forming of the conductive metal material over the substrate; and wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
3. The method of claim 1 , wherein the forming of the conductive metal material comprises depositing the metal material over the substrate and removing portions of the deposited metal material using a chemical-mechanical polish process.
4. A method of forming a semiconductor device, comprising:
forming a memory cell on a substrate by:
forming a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
forming a conductive erase gate over and insulated from the first source region,
forming a conductive floating gate over and insulated from a first portion of the first channel region,
forming a conductive control gate over and insulated from the conductive floating gate, and
forming a conductive word line gate over and insulated from a second portion of the first channel region;
forming a first logic device on the substrate by:
forming a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region, and
forming a conductive first logic gate over and insulated from the second channel region;
forming a second logic device on the substrate by:
forming a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region, and
forming a conductive second logic gate over and insulated from the third channel region;
wherein the forming of the conductive word line gate, the forming of the conductive first logic gate, and the forming of the conductive second logic gate comprise forming a conductive metal material over the substrate;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation formed over the substrate and by a second insulation formed over the substrate;
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the first insulation is a first layer of silicon dioxide; and
wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
5. A method of forming a semiconductor device, comprising:
forming a memory cell on a substrate by:
forming a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
forming a conductive erase gate over and insulated from the first source region,
forming a conductive floating gate over and insulated from a first portion of the first channel region,
forming a conductive control gate over and insulated from the conductive floating gate, and
forming a conductive word line gate over and insulated from a second portion of the first channel region;
forming a first logic device on the substrate by:
forming a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region, and
forming a conductive first logic gate over and insulated from the second channel region;
forming a second logic device on the substrate by:
forming a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region, and
forming a conductive second logic gate over and insulated from the third channel region;
wherein the forming of the conductive word line gate, the forming of the conductive first logic gate, and the forming of the conductive second logic gate comprise forming a conductive metal material over the substrate;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation formed over the substrate and by a second insulation formed over the substrate;
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the conductive erase gate is insulated from the first source region by the first insulation and by a third insulation; and
wherein the first insulation is a first layer of silicon dioxide, the second insulation is a second layer of silicon dioxide and a layer of high K material, and the third insulation is a third layer of silicon dioxide.
6. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory cell that comprises:
a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
a conductive erase gate disposed over and insulated from the first source region,
a conductive floating gate disposed over and insulated from a first portion of the first channel region,
a conductive control gate disposed over and insulated from the conductive floating gate, and
a conductive word line gate disposed over and insulated from a second portion of the first channel region;
a first logic device that comprises:
a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region,
a conductive first logic gate disposed over and insulated from the second channel region;
a second logic device that comprises:
a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region,
a conductive second logic gate disposed over and insulated from the third channel region;
wherein the conductive word line gate, the conductive first logic gate, and the conductive second logic gate all comprise a same conductive metal material;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation disposed over the substrate and by a second insulation disposed over the substrate;
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the conductive erase gate is insulated from the first source region by the first insulation and by a third insulation, and not by the second insulation;
wherein the conductive floating gate is insulated from the first portion of the first channel region by the first insulation and not by the second insulation and not by the third insulation; and
wherein the conductive word line gate is insulated from the second portion of the first channel region by the first insulation and by the second insulation and not by the third insulation; and wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
7. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory cell that comprises:
a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
a conductive erase gate disposed over and insulated from the first source region,
a conductive floating gate disposed over and insulated from a first portion of the first channel region,
a conductive control gate disposed over and insulated from the conductive floating gate, and
a conductive word line gate disposed over and insulated from a second portion of the first channel region;
a first logic device that comprises:
a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region,
a conductive first logic gate disposed over and insulated from the second channel region;
a second logic device that comprises:
a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region,
a conductive second logic gate disposed over and insulated from the third channel region;
wherein the conductive word line gate, the conductive first logic gate, and the conductive second logic gate all comprise a same conductive metal material;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation disposed over the substrate and by a second insulation disposed over the substrate; and
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the conductive erase gate comprises the same conductive metal material; and wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
8. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory cell that comprises:
a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
a conductive erase gate disposed over and insulated from the first source region,
a conductive floating gate disposed over and insulated from a first portion of the first channel region,
a conductive control gate disposed over and insulated from the conductive floating gate, and
a conductive word line gate disposed over and insulated from a second portion of the first channel region;
a first logic device that comprises:
a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region,
a conductive first logic gate disposed over and insulated from the second channel region;
a second logic device that comprises:
a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region,
a conductive second logic gate disposed over and insulated from the third channel region;
wherein the conductive word line gate, the conductive first logic gate, and the conductive second logic gate all comprise a same conductive metal material;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation disposed over the substrate and by a second insulation disposed over the substrate; and
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the first insulation is a first layer of silicon dioxide; and
wherein the second insulation is a second layer of silicon dioxide and a layer of high K material.
9. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory cell that comprises:
a first source region and a first drain region in the substrate, where a first channel region of the substrate is disposed between the first source region and the first drain region,
a conductive erase gate disposed over and insulated from the first source region,
a conductive floating gate disposed over and insulated from a first portion of the first channel region,
a conductive control gate disposed over and insulated from the conductive floating gate, and
a conductive word line gate disposed over and insulated from a second portion of the first channel region;
a first logic device that comprises:
a second source region and a second drain region in the substrate, where a second channel region of the substrate is disposed between the second source region and the second drain region,
a conductive first logic gate disposed over and insulated from the second channel region;
a second logic device that comprises:
a third source region and a third drain region in the substrate, where a third channel region of the substrate is disposed between the third source region and the third drain region,
a conductive second logic gate disposed over and insulated from the third channel region;
wherein the conductive word line gate, the conductive first logic gate, and the conductive second logic gate all comprise a same conductive metal material;
wherein the conductive second logic gate is insulated from the third channel region by a first insulation disposed over the substrate and by a second insulation disposed over the substrate; and
wherein the conductive first logic gate is insulated from the second channel region by the second insulation and not by the first insulation;
wherein the conductive erase gate is insulated from the first source region by the first insulation and by a third insulation; and
wherein the first insulation is a first layer of silicon dioxide, the second insulation is a second layer of silicon dioxide and a layer of high K material, and the third insulation is a third layer of silicon dioxide.