Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing
View Patent ↗A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart trenches. Within each trench, at the bottom thereof is a region of a second conductivity. A channel extends from one of the region at the bottom of one of the trenches along the side wall of that trench to the top planar surface of the substrate, and along the sidewall of the adjacent trench to the region at the bottom of the adjacent trench. The trapping layer is along the sidewall of each of the two trenches. A control gate is in each of the trenches capacitively coupled to the trapping layer along the sidewall and to the region at the bottom of the trench. Each of the trenches can stored a plurality of bits.
1. A non-volatile memory cell comprising:
a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface;
a first trench in said substrate extending in a first direction, said first trench having a sidewall and a bottom;
a first region of a second conductivity type in said bottom of said first trench;
a second trench in said substrate extending in the first direction parallel to and spaced apart from the first trench by a section along the planar surface, said second trench having a sidewall and a bottom;
a second region of the second conductivity type in said bottom of said second trench;
a channel region connecting said first and second regions for the conduction of charges, said channel region having three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; a third portion along the section between the first and second trenches, near the planar surface;
a first charge trapping layer spaced apart from the first portion of the channel region for trapping charges;
a second charge trapping layer spaced apart from the second portion of the channel region for trapping charges;
a dielectric layer spaced apart from the third portion of the channel region;
a first control gate in the first trench extending in the first direction, capacitively coupled to the first charge trapping layer and to the first region;
a second control gate in the second trench extending in the first direction, capacitively coupled to the second charge trapping layer and to the second region; and
a third control gate couple to the dielectric layer for controlling the conduction of charges in the third portion of the channel region.
2. The cell of claim 1 wherein the third control gate extends in a second direction substantially perpendicular to the first direction.
3. The cell of claim 2 wherein said first and second charge trapping layer is a material made from Si-nc in SiN or silicon nitride or nanocrystal.
4. The cell of claim 1 wherein said substrate is single crystalline silicon.
5. An array of non-volatile memory cells comprising:
a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface;
a plurality of spaced apart trenches in said substrate extending in a first direction, each trench separated from an adjacent trench by a section along the planar surface, with each trench having a sidewall and a bottom;
a plurality of non-volatile memory cells arranged in a plurality of rows and columns in said substrate, with the rows extending in the first direction and each row substantially perpendicular to each column; each of said non-volatile memory cell comprises:
a first trench having a first region of a second conductivity type in said bottom of said first trench;
a second trench, immediately adjacent to and spaced apart from the first trench, said second trench having a second region of the second conductivity type in said bottom of the second trench;
a channel region connecting the region along the bottom of the first trench to the region along the bottom of the second trench, for the conduction of charges, said channel region having three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; a third portion along the section between the first trench and the second trench, near the planar surface;
a first charge trapping layer spaced apart from the first portion of the channel region for trapping charges;
a second charge trapping layer spaced apart from the second portion of the channel region for trapping charges;
a dielectric layer spaced apart from the third portion of the channel region;
a first control gate in the first trench extending in the row direction, capacitively coupled to the first charge trapping layer and to the first region;
a second control gate in the second trench extending in the row direction, capacitively coupled to the second charge trapping layer and to the second region;
a third control gate couple to the dielectric layer for controlling the conduction of charges in the third portion of the channel region, said third control gate extending in the column direction;
wherein non-volatile memory cells adjacent to one another in the row direction to one side share a common first control gate, and a common first region; and cells adjacent to one another in the row direction to another side share a common second control gate, and a common second region; and
wherein non-volatile memory cells in the same column direction share a common third control gate.
6. The array of claim 5 wherein said first and second charge trapping layer is Si-nc in SiN.
7. The array of claim 6 wherein each of said first and second charge trapping layer is spaced apart from the substrate by a first insulating layer.
8. The array of claim 7 wherein the first and second control gates are spaced apart from the first and second charge trapping layers, respectively, by a second insulating layer.
9. The array of claim 8 wherein said first insulating layer is silicon dioxide.
10. The array of claim 9 wherein said second insulating layer is ONO.
11. A method of programming a non-volatile memory cell of the type having a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface, with a first trench in said substrate extending in a first direction, said first trench having a sidewall and a bottom; a first region of a second conductivity type in said bottom of said first trench; a second trench in said substrate extending in the first direction parallel to and spaced apart from the first trench by a section along the planar surface, said second trench having a sidewall and a bottom; a second region of the second conductivity type in said bottom of said second trench; a channel region connecting said first and second regions for the conduction of charges, said channel region having three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; a third portion along the section between the first and second trenches, near the planar surface; a first charge trapping layer spaced apart from the first portion of the channel region for trapping charges; a second charge trapping layer spaced apart from the second portion of the channel region for trapping charges; a dielectric layer spaced apart from the third portion of the channel region; a first control gate in the first trench extending in the first direction, capacitively coupled to the first charge trapping layer and to the first region; a second control gate in the second trench extending in the first direction, capacitively coupled to the second charge trapping layer and to the second region; and a third control gate couple to the dielectric layer for controlling the conduction of charges in the third portion of the channel region; wherein said method comprising:
applying a first voltage to the first region;
applying a second voltage to the first control gate; said second voltage sufficient to turn on the first portion of the channel region irrespective of the state of charge in the first charge trapping layer;
applying a third voltage to the third control gate, said third voltage sufficient to turn on the third portion of the channel region;
applying a fourth voltage to the second control gate, said fourth voltage greater than the second voltage;
applying a fifth voltage to the second region, said fifth voltage is greater than the first voltage and is sufficient to attract charges from the first region; wherein charges are injected to the second charge trapping layer near the planar surface from the channel region near the third portion;
applying a sixth voltage to the second region, said sixth voltage is greater than the first voltage and is sufficient to attract charges from the first region, and is less than the sixth voltage;
wherein charges are injected to the second charge trapping layer near the second region from the second portion of the channel region;
applying the first voltage to the second region;
applying the second voltage to the second control gate; said second voltage sufficient to turn on the second portion of the channel region irrespective of the state of charge in the second charge trapping layer;
applying the third voltage to the third control gate, said third voltage sufficient to turn on the third portion of the channel region;
applying the fourth voltage to the first control gate, said fourth voltage greater than the second voltage;
applying the fifth voltage to the first region, said fifth voltage is greater than the first voltage and is sufficient to attract charges from the second region; wherein charges are injected to the first charge trapping layer near the planar surface from the channel region near the third portion;
applying the sixth voltage to the first region, said sixth voltage is greater than the first voltage and is sufficient to attract charges from the second region, and is less than the sixth voltage; wherein charges are injected to the first charge trapping layer near the first region from the first portion of the channel region;
whereby four bits can be programmed into a single memory cell.
12. The method of claim 11 wherein charges are injected to the second charge trapping layer near the planar surface from the channel region near the third portion and charges are injected to the first charge trapping layer near the planar surface from the channel region near the third portion by the mechanism of source side injection.
13. The method of claim 11 wherein charges are injected to the second charge trapping layer near the second region from the second portion of the channel region and charges are injected to the first charge trapping layer near the first region from the first portion of the channel region by the mechanism of hot channel injection.
14. A method of programming a non-volatile memory cell of the type having a substrate of a substantially single crystalline semiconductive material having a first conductivity type and a planar surface, with a first trench in said substrate extending in a first direction, said first trench having a sidewall and a bottom; a first region of a second conductivity type in said bottom of said first trench; a second trench in said substrate extending in the first direction parallel to and spaced apart from the first trench by a section along the planar surface, said second trench having a sidewall and a bottom; a second region of the second conductivity type in said bottom of said second trench; a channel region connecting said first and second regions for the conduction of charges, said channel region having three portions: a first portion along the sidewall of the first trench, a second portion along the sidewall of the second trench; a third portion along the section between the first and second trenches, near the planar surface; a first charge trapping layer spaced apart from the first portion of the channel region for trapping charges; a second charge trapping layer spaced apart from the second portion of the channel region for trapping charges; a dielectric layer spaced apart from the third portion of the channel region; a first control gate in the first trench extending in the first direction, capacitively coupled to the first charge trapping layer and to the first region; a second control gate in the second trench extending in the first direction, capacitively coupled to the second charge trapping layer and to the second region; and a third control gate couple to the dielectric layer for controlling the conduction of charges in the third portion of the channel region; wherein said method comprising:
applying a first voltage to the first region;
applying a second voltage to the first control gate; said second voltage sufficient to turn on the first portion of the channel region irrespective of the state of charge in the first charge trapping layer;
applying a third voltage to the third control gate, said third voltage sufficient to turn on the third portion of the channel region;
applying a fourth voltage to the second control gate, said fourth voltage greater than the second voltage;
applying a fifth voltage to the second region, said fifth voltage is greater than the first voltage and is sufficient to attract charges from the first region; wherein charges are injected to the second charge trapping layer near the planar surface from the channel region near the third portion;
applying a sixth voltage to the second region, said sixth voltage is greater than the first voltage and is sufficient to attract charges from the first region, and is less than the sixth voltage;
wherein charges are injected to the second charge trapping layer near the second region from the second portion of the channel region;
applying the first voltage to the second region;
applying the second voltage to the second control gate; said second voltage sufficient to turn on the second portion of the channel region irrespective of the state of charge in the second charge trapping layer;
applying the third voltage to the third control gate, said third voltage sufficient to turn on the third portion of the channel region;
applying the fourth voltage to the first control gate, said fourth voltage greater than the second voltage;
applying the fifth voltage to the first region, said fifth voltage is greater than the first voltage and is sufficient to attract charges from the second region; wherein charges are injected to the first charge trapping layer near the planar surface from the channel region near the third portion;
applying the sixth voltage to the first region, said sixth voltage is greater than the first voltage and is sufficient to attract charges from the second region, and is less than the sixth voltage; wherein charges are injected to the first charge trapping layer near the first region from the first portion of the channel region;
whereby four bits can be programmed into a single memory cell.