Sub volt flash memory system
View Patent ↗Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
1. A bitline sensing load circuit comprising:
a diode connected MOS transistor including a first terminal for coupling to a first voltage supply, including a second terminal for coupling to a memory cell terminal and for providing a voltage indicative of the content stored in said memory cell, and further including a bulk voltage terminal, locally provided, for coupling to a second voltage supply, the second voltage supply having a voltage different from the first voltage supply and having a voltage different from ground; and
a bipolar junction transistor including an emitter and a collector coupled between the memory cell terminal and a third supply voltage terminal and the memory cell terminal for applying a preemphasis voltage on the memory cell terminal before sensing a voltage on the memory cell terminal indicative of content of a memory cell coupled thereto.
2. The circuit of claim 1 , wherein the diode connected MOS transistor is a PMOS transistor.
3. The circuit of claim 2 , wherein the bipolar junction transistor is an npn transistor.
4. The circuit of claim 2 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the PMOS transistor and a second terminal for coupling to the memory cell terminal.
5. The circuit of claim 3 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the diode connected MOS transistor and a second terminal for coupling to the memory cell terminal.
6. The circuit of claim 1 , wherein the bipolar junction transistor is an npn transistor.
7. The circuit of claim 6 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the diode connected MOS transistor and a second terminal for coupling to the memory cell terminal.
8. The circuit of claim 1 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the diode connected MOS transistor and a second terminal for coupling to the memory cell terminal.
9. A memory system comprising:
a memory cell;
a first voltage supply;
a second voltage supply;
a third voltage supply;
a bitline sensing load circuit comprising:
a diode connected MOS transistor including a first terminal coupled to the first voltage supply, a second terminal coupled to the memory cell and providing a voltage indicative of the content stored in said memory cell, and further including a bulk voltage terminal coupled to the second voltage supply, the second voltage supply having a voltage different from the first voltage supply and having a voltage different from ground; and
a bipolar junction transistor including an emitter and a collector coupled between the memory cell and the third supply voltage for applying a preemphasis voltage on the second terminal of the diode connected MOS transistor.
10. The system of claim 9 , wherein the diode connected MOS transistor is a PMOS transistor.
11. The system of claim 10 , wherein the bipolar junction transistor is an npn transistor.
12. The system of claim 10 , wherein the memory cell is a multi-level memory cell.
13. The system of claim 10 , wherein the second voltage supply provides a voltage less than the pn forward junction voltage of the PMOS transistor.
14. The system of claim 10 , wherein the second voltage supply provides a voltage greater than the pn forward junction voltage of the PMOS transistor.
15. The circuit of claim 10 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the PMOS transistor and a second terminal for coupling to the memory cell.
16. The system of claim 11 , wherein the memory cell is a multi-level memory cell.
17. The system of claim 9 , wherein the bipolar junction transistor is an npn transistor.
18. The system of claim 17 , wherein the memory cell is a multi-level memory cell.
19. The system of claim 9 , wherein the memory cell is a multi-level memory cell.
20. The circuit of claim 9 further comprising an NMOS transistor including a first terminal coupled to the second terminal of the diode connected MOS transistor and a second terminal for coupling to the memory cell.