Array of non-volatile memory cells with ROM cells
View Patent ↗A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.
1. A memory device comprising:
a semiconductor substrate;
a plurality of ROM cells, wherein each of the ROM cells comprises:
spaced apart source and drain regions formed in the substrate, with a channel region therebetween,
a first gate disposed over and insulated from a first portion of the channel region,
a second gate disposed over and insulated from a second portion of the channel region,
wherein for each of a first subgroup of the plurality of ROM cells, the ROM cell includes a higher voltage threshold implant region in the channel region; and
wherein for each of a second subgroup of the plurality of ROM cells, the ROM cell lacks any higher voltage threshold implant region in the channel region; and
a plurality of NVM cells, wherein each of the NVM cells comprises:
spaced apart second source and second drain regions formed in the substrate, with a second channel region therebetween,
a floating gate disposed over and insulated from a first portion of the second channel region,
a select gate disposed over and insulated from a second portion of the channel region.
2. The memory device of claim 1 , wherein each of the NVM cells further comprises:
a control gate disposed over and insulated from the floating gate; and
an erase gate disposed over and insulated from the second source region.
3. The memory device of claim 1 , wherein for each of the first subgroup of the plurality of ROM cells, the higher voltage threshold implant region extends from the source region toward, but does not reach, the drain region.
4. The memory device of claim 1 , wherein each of the ROM cells further comprises:
a third gate disposed over and electrically coupled to the first gate.
5. The memory device of claim 1 , wherein each of the ROM cells further comprises:
a third gate disposed over and insulated from the first gate.
6. The memory device of claim 5 , wherein for each of the second subgroup of the plurality of ROM cells, the higher voltage threshold implant region is disposed under the second gate.