Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements
View Patent ↗A differential sensing content addressable memory cell without any word lines connected to the cells in the same row comprises a first bit line for supplying a first bit. A first storage element has a first phase change resistor for storing a first stored bit, which is connected in series with a first diode. The first storage element is connected to the first bit line. A second bit line supplies a second bit, with the second bit being an inverse of the first bit. A second storage element has a second phase change resistor for storing a second stored bit, which is connected in series with a second diode. The second storage element is connected to the second bit line. A match line is connected to the first and second storage elements for indicating whether a match occurred between the first bit and the first stored bit, and between the second bit and the second stored bit
1. A content addressable memory cell comprising:
a first bit line for supplying a first bit;
a first storage element of a first phase change resistor for storing a first stored bit, connected in series with a first diode; said first storage element connected to said first bit line;
a second bit line for supplying a second bit, said second bit being an inverse of said first bit;
a second storage element of a second phase change resistor for storing a second stored bit, connected in series with a second diode; said second storage element connected to said second bit line; and
a match line connected to said first and second storage elements for indicating whether a match occurred between said first bit and said first stored bit, and between said second bit and said second stored bit.
2. The cell of claim 1 wherein each of said first and second phase change resistor is made of chalcogenide material.
3. The cell of claim 2 wherein each cell is capable of storing one of three possible states:
a first state representing a data bit of “1” wherein the first stored bit represents a bit “1” and the second stored bit represents a bit “0”;
a second state representing a data bit of “0” wherein the first stored bit represents a bit “0” and the second stored bit represents a bit “1”;
a third state representing a “don't care” state wherein the first stored bit represents a bit “0” and the second stored bit represents a bit “0”.
4. The cell of claim 1 wherein said first diode connects said first phase change resistor to said match line; and
wherein said second diode connects said second phase change resistor to said match line.
5. The cell of claim 1 wherein said first diode connects said first phase change resistor to said first bit line; and
wherein said second diode connects said second phase change resistor to said second bit line.
6. An array of content addressable memory cells comprising:
a plurality of content addressable memory cells arranged in a plurality of rows and columns;
a plurality of pairs of bit lines arranged in columns; each pair of bit lines for supplying a first bit and a second bit with said second bit being an inverse of said first bit; a pair of bit lines being supplied to the cells arranged in the same column;
a plurality of match lines, wherein each match line is connected to the cells arranged in the same row; and
wherein each cell comprises:
a first storage element of a first phase change resistor for storing a first stored bit, connected in series with a first diode;
a second storage element of a second phase change resistor for storing a second stored bit, connected in series with a second diode;
wherein the first storage element is connected to an associated match line and to one of a pair of associated bit lines; and
wherein each of the second storage element is connected to said associated match line and to another of said pair of associated bit lines.
7. The cell of claim 6 wherein each of said first and second phase change resistors is made of chalcogenide material.
8. The cell of claim 7 wherein each cell is capable of storing one of three possible states:
a first state representing a data bit of “1” wherein the first stored bit represents a bit “1” and the second stored bit represents a bit “0”;
a second state representing a data bit of “0” wherein the first stored bit represents a bit “0” and the second stored bit represents a bit “1”;
a third state representing a “don't care” state wherein the first stored bit represents a bit “0” and the second stored bit represents a bit “0”.
9. The array of claim 6 wherein said first diode connects said first phase change resistor to an associated match line; and
wherein said second diode connects said second phase change resistor to said associated match line.
10. The array of claim 6 wherein said first diode connects said first phase change resistor to one of a pair of associated bit lines; and
wherein said second diode connects said second phase change resistor to another of said pair of associated bit lines.