Single transistor sensing and double transistor sensing for flash memory
View Patent ↗A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.
1. A sensing system for a memory comprising:
a cancellation circuit to generate a cancellation signal to offset a leakage current on a memory cell line;
a pull-up load selectively coupled to the memory cell line; and
a differential amplifier coupled to the memory cell line and the cancellation circuit.
2. The sensing system of claim 1 wherein the pull-up load is a PMOS transistor.
3. The sensing system of claim 1 wherein the pull-up load is a resistor.
4. The sensing system of claim 1 wherein the differential amplifier includes an autozero circuit.
5. The sensing system of claim 1 wherein said cancellation circuit includes a holding capacitor.
6. The sensing system of claim 1 further comprising a current source coupled to said memory cell during voltage mode sensing.
7. The sensing system of claim 1 comprising a resistor divider coupled to said differential amplifier to generate a reference voltage.
8. The sensing system of claim 1 further comprising a charge compensated switch to provide said selective coupling.
9. A serial sensing system for a memory comprising:
a cancellation circuit to generate a cancellation signal to offset a leakage current on a memory cell line; and
a differential amplifier coupled to the memory cell line and the cancellation circuit.
10. The sensing system of claim 9 wherein the cancellation circuit generates a cancellation signal to offset a leakage current on a reference memory cell line and the memory cell line is selectively and serially coupled to a plurality of data memory cell lines.
11. The sensing system of claim 9 wherein the cancellation circuit generates a cancellation signal to offset a leakage current on a data memory cell line and the memory cell line is selectively and serially coupled to a plurality of reference memory cell lines.
12. The sensing system of claim 9 further comprising a charge compensated switch to selectively couple said cancellation circuit to the memory cell line.
13. A sensing system for a memory comprising:
a cancellation circuit to detect and cancel capacitance mismatch on a reference memory cell bitline and a data memory cell bitline; and
a bias circuit selectively coupled to a reference memory cell terminal and to a data memory cell terminal, the reference memory cell terminal and the data memory cell terminal being selectively coupled to the reference memory cell bitline and the data memory cell bitline, respectively.
14. The sensing system of claim 13 wherein the bias circuit is loadless.
15. The sensing system of claim 13 wherein the bias circuit is a load circuit.
16. The sensing system of claim 13 further comprising a differential amplifier including first and second inputs coupled to the reference memory cell terminal and the data memory cell terminal, respectively.
17. The sensing system of claim 16 wherein the differential amplifier includes autozero.
18. The sensing system of claim 13 further comprising a differential amplifier including first and second inputs capacitively coupled to the reference memory cell terminal and the data memory cell terminal, respectively.
19. The sensing system of claim 13 further including a cancellation circuit to generate a cancellation signal to offset leakage currents on the data memory cell bitline and the reference memory cell bitline.
20. The sensing system of claim 13 further comprising a plurality of charge compensated switches to selectively couple the reference memory cell terminal and the data memory cell terminal to the reference memory cell bitline and the data memory cell bitline, respectively.
21. The sensing system of claim 13 wherein sensing of the reference memory cell bitline and the data memory cell bitline is dynamic sensing.
22. A method of sensing a memory comprising:
detecting capacitance mismatch on a first memory cell bitline and a second memory cell bitline; and
canceling said capacitance mismatch.
23. The method of claim 22 further comprising differentially comparing voltages on said first and second memory bit lines.
24. The method of 23 further comprising comparing voltages in an autozero mode.
25. The method of 22 further comprising autozeroing the bitlines prior to said comparing.
26. The method of claim 22 further comprising dynamic sensing of said bitlines.
27. A sensing system for a memory comprising:
a first differential current source generating a first differential current in response to a reference current sensed on a reference memory cell line relative to a data current sensed on a data memory cell line;
a second differential current source generating a differential current in response to the data current sensed on the data memory cell line relative to reference current sensed on the reference memory cell line; and
a differential voltage amplifier including first and second inputs coupled to the first and second differential current sources, respectively.
28. The sensing system of claim 27 wherein the differential amplifier includes autozero.
29. The sensing system of claim 27 further including a cancellation circuit to generate a cancellation signal to offset leakage currents on the data memory cell line and the reference memory cell line.
30. A sensing system in claim 27 further comprising a plurality of charge compensated switches to selectively couple the first and second differential current sources to the differential voltage amplifier.
31. The sensing system of claim 27 wherein sensing of the reference memory cell line and the data memory cell line is dynamic sensing.
32. The sensing system of claim 27 wherein the differential voltage amplifier is capacitively coupled to the first and second differential current sources.