NOR flash memory
View Patent ↗Semiconductor memory array and process of fabrication in which a plurality of bit line diffusions are formed in a substrate, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates beside the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate, and at least one additional conductor capacitively coupled to the floating gates. In some disclosed embodiments, the conductors adjacent to the bit line diffusions are word lines, and the additional conductors consist of either a pair of coupling gates which are coupled to respective ones of the floating gates or a single coupling gate which is coupled to both of the floating gates. In another embodiment, the conductors adjacent to the bit line diffusions are program lines, and the third conductors are word lines which extend in a direction perpendicular to the program lines and the diffusions.
1. A memory cell array, comprising: a substrate, first and second bit line diffusions in the substrate, first and second word lines adjacent to the bit line diffusions, a source line diffusion in the substrate midway between the bit line diffusions, an erase gate above the source line diffusion, first and second floating gates disposed between the word lines and the erase gate and having a height greater than the word lines and the erase gate, coupling gates overlying the floating gates and edge portions of the word lines and the erase gate, a bit line extending in a direction perpendicular to the word lines, and bit line contacts interconnecting the bit line diffusions and the bit line.
2. The memory cell array of claim 1 wherein the coupling gates are wider than the floating gates, and lower portions of the coupling gates overlap and embrace upper side portions of the floating gates to provide capacitive coupling between the coupling gates and the upper side portions of the floating gates as well as between the coupling gates and the top surfaces of the floating gates.
3. The memory cell array of claim 1 wherein a positive voltage is applied to the erase gate and a negative voltage is applied to the coupling gate of a selected cell to produce electron tunneling from the floating gate to the erase gate.
4. The memory cell array of claim 1 including a gate oxide between the erase gate and the source line diffusion of sufficient thickness that the erase gate can sustain a voltage high enough to produce electron tunneling from one of the floating gates to the erase gate without causing breakdown of the gate oxide.
5. The memory cell array of claim 4 wherein the gate oxide has a thickness on the order of 150 Å to 250 Å, and a voltage on the order of 10-15V is applied to the erase gate.
6. A memory cell array, comprising: a substrate, a plurality of bit line diffusions in the substrate, bit lines extending in a first direction above the bit line diffusions, and memory cells formed in pairs between the bit line diffusions, with each of the pairs of cells having word lines adjacent to the bit line diffusions and perpendicular to the bit lines, floating gates disposed beside and having a height greater than the word lines, at least one coupling gate capacitively coupled to the floating gates and overlying portions of the word lines, an erase gate between the floating gates, a source line diffusion in the substrate beneath the erase gate, and bit line contacts interconnecting the bit line diffusions and one of the bit lines.
7. The memory cell array of claim 6 wherein separate coupling gates are coupled to the floating gates in the two cells in each pair.
8. The memory cell array of claim 7 wherein lower portions of the coupling gates overlap and embrace upper side portions of the floating gates to provide capacitive coupling between the coupling gates and the upper side portions of the floating gates as well as between the coupling gates and the top surfaces of the floating gates.
9. The memory cell array of claim 6 wherein a single coupling gate is coupled to the floating gates in the two cells in each pair.
10. The memory cell array of claim 9 wherein the coupling gate has a central trunk and a plurality of fingers extending from the trunk and overlying the floating gates.
11. The memory cell array of claim 9 wherein lower portions of the coupling gate overlap and embrace upper portions of the floating gates to provide extended capacitive coupling between the coupling gate and the floating gates.
12. A memory cell array, comprising: a substrate; a plurality of bit line diffusions in the substrate; memory cells formed in pairs between the bit line diffusions, each of the pairs of cells having first and second conductors adjacent to the bit line diffusions, floating gates disposed beside and having a height greater than the first and second conductors, an erase gate between the floating gates, and a source line diffusion in the substrate beneath the erase gate; and at least one additional conductor overlapping and embracing upper side portions of the floating gates to provide capacitive coupling between the coupling gates and the upper side portions of the floating gates as well as between the coupling gates and the top surfaces of the floating gates.
13. The memory cell array of claim 12 wherein the at least one additional conductor includes a pair of coupling gates which extend in a direction parallel to the erase gate and are coupled to respective ones of the floating gates in the pair.
14. The memory cell array of claim 12 wherein the at least one additional conductor is a single coupling gate which extends in a direction parallel to the erase gate and is coupled to both of the floating gates in the pair.
15. The memory cell array of claim 12 wherein the at least one additional conductor is a word line which extends in a direction perpendicular to the first and second conductors and is coupled to both of the floating gates in the pair.
16. A memory cell array comprising: a substrate of a first conductivity type, first and second spaced apart regions of a second conductivity type in the substrate, first and second word lines adjacent to the first and second regions, a third region of the second conductivity type in the substrate between the first and second regions, an erase gate above the third region, first and second floating gates disposed between the word lines and the erase gate and extending to a greater height than the word lines and the erase gate, coupling gates overlying the floating gates, a bit line extending in a direction perpendicular to the word line, and bit line contacts interconnecting the first and second regions and the bit line.
17. A memory cell array, comprising: a substrate; a plurality of diffusions in the substrate; memory cells formed in pairs between the diffusions, with each of the pairs of cells having first and second conductors adjacent to the diffusions, floating gates disposed beside and extending to a greater height than the first and second conductors, an erase gate between the floating gates, and an additional diffusion in the substrate beneath the erase gate; and at least one additional conductor capacitively coupled to the floating gates.