Landing pad for use as a contact to a conductive spacer
View Patent ↗A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.
1. A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device, said landing pad comprising:
two islands, each substantially rectangularly shaped and spaced apart from one another and from the structure; and
conductive spacers adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure;
wherein contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.
2. The landing pad of claim 1 wherein said conductive spacers are made of conductive polysilicon.
3. The landing pad of claim 2 wherein the islands are spaced apart form one another by a distance which is less than twice the width of each conductive spacer.
4. The landing pad of claim 3 wherein the islands are spaced apart from the structure by a distance which is less than twice the width of each conductive spacer.
5. A non-volatile memory device comprising:
an array of non-volatile memory cells arranged in a plurality of rows and columns wherein cells in the same row are connected by a common spacer shaped control gate adjacent a structure;
a plurality of spaced apart landing pads adjacent each control gate, each landing pad comprising two substantially rectangularly shaped spaced apart islands, each having a spacer adjacent to the island, wherein the spacer adjacent to one island overlaps the spacer adjacent the other island, and wherein the spacers of the islands overlap the adjacent common spacer shaped control gate;
a layer of insulating material covering the spacers of the islands, the common spacer shaped control gate and the islands, with the insulating material having a hole through the insulating material, said hole positioned between the islands and between the islands and the structure;
a conductive layer on the layer of insulating material connecting through the hole to the control gate.
6. The memory device of claim 5 wherein the common spacer shaped control gate is made of conductive polysilicon.
7. The memory device of claim 6 wherein the spacers adjacent to the islands are made of conductive polysilicon.
8. The memory device of claim 7 wherein the structure comprises:
a floating gate insulated from the control gate by a tunneling material; said floating gate having a tip for facilitating the tunneling of charges from the floating gate through the tunneling material to the control gate.
9. The memory device of claim 8 wherein the array comprises a plurality of spaced apart control gates, each gate extending in the row direction and wherein the distance of separation between each adjacent control gate is greater at the location with the landing pad therebetween than at the location without the landing pad.
10. The memory device of claim 9 wherein an isolation region separates each column of cells.