Granted Patent B2

US 9,633,735 · App. 14/486,687 · Granted Apr 25, 2017

Abstract

Claims (6)

1. A method of erasing a portion of a sector of a flash memory system, the sector comprising a first row of flash memory cells and a second row of flash memory cells, wherein the first row and second row share an erase gate, comprising:

applying a first non-zero bias voltage to a control gate for the first row, wherein the first non-zero bias voltage is around 9 volts;

applying a second non-zero bias voltage to a control gate for the second row, wherein the second non-zero bias voltage is around −9 volts;

applying a third non-zero bias voltage to a word line for the second row, wherein the third non-zero bias voltage is within the range of 0.8 to 5 volts; and

applying a signal to the erase gate to erase the first row while not erasing the second row.

2. The method of claim 1 , wherein the first row of flash memory cells and the second row of flash memory cells each comprise split gate flash memory cells.

Assignments (15)