Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
View Patent ↗Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
1. A sensing circuit comprising:
a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; and
a first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; and
a second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor;
wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage;
wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first and second regions are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region; and
a gate portion above the insulating layer;
wherein each insulating portion characterizes a threshold voltage between the gate and the first region or the second region adjacent each insulating portion; and
wherein the first insulating portion is fabricated with varying dimension including a first thickness different than a second thickness of the second insulating portion to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.
2. The sensing circuit of claim 1 further comprising one or more additional memory columns.
3. The sensing circuit of claim 1 wherein the first differential threshold NMOS transistor is a cascoding transistor.
4. The sensing circuit of claim 1 wherein one or more of the differential threshold transistor(s) is/are cascoding transistor(s).
5. The sensing circuit of claim 1 , wherein one or more of the differential threshold MOS transistors are transistors having a channel region including a first junction region and a second junction region, wherein shape of the first insulating portion or shape or implantation of the first junction region are of varying dimension to provide a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage specified via dimension of one or both of the second insulating portion and/or the second junction region.
6. The sensing circuit of claim 1 wherein one or more of the differential threshold transistors includes a channel region comprising junction regions including a first junction region adjacent the first region and a second junction region adjacent the second region, the first junction region and the second junction region being opposed from each other; and
wherein one or both of shape or implantation of the first junction region or the second junction region are of varying dimension to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed junction region.
7. The sensing circuit of claim 1 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
a charge trapping region that yields a first threshold voltage associated with the first region or a second threshold voltage associated with the second region.
8. The circuit of claim 1 wherein the first thickness is varied via removal of an offset region from the insulating layer.
9. The circuit of claim 1 wherein the first insulating portion is varied to provide for the differing first threshold voltage.
10. The circuit of claim 1 wherein a width of the first insulating portion is varied to provide for the differing first threshold voltage.
11. The circuit of claim 1 wherein the first insulating portion includes a region of oxide material removed from the insulating layer to effect a threshold voltage that differs from the second threshold voltage of the second insulating portion.
12. The sensing circuit of claim 1 wherein one or more of the differential threshold MOS transistors are transistors having a channel region including a first junction region and a second junction region, wherein shape of the first insulating portion or shape or implantation of the first junction region are of varying dimension to provide a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage specified via dimension of one or both of the second insulating portion and/or the second junction region.
13. The sensing circuit of claim 1 wherein one or more of the differential threshold transistors includes a channel region comprising junction regions including a first junction region adjacent the first region and a second junction region adjacent the second region, the first junction region and the second junction region being opposed from each other; and
wherein one or both of shape or implantation of the first junction region or the second junction region are of varying dimension to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed junction region.
14. The sensing circuit of claim 1 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
a charge trapping region that yields a first threshold voltage associated with the first region or a second threshold voltage associated with the second region.
15. The sensing circuit of claim 1 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region, and wherein each insulating portion defines a threshold voltage between the gate and the first region or the second region associated with each insulating portion; and
a gate portion above the insulating layer;
wherein the first insulating portion or the second insulating portion is fabricated of varying length and width, and of different dimension than the opposed insulating portion, to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.
16. A sensing circuit comprising:
a data column including an output voltage node, a memory cell, a first PMOS transistor that is diode-connected, and a first differential threshold NMOS transistor having a drain connected to a drain of the first PMOS transistor to form the output voltage node and a source connected to a first node; and
a first memory column comprising a second differential threshold NMOS transistor having a drain connected to the first node; and
a second memory column connected to the first node in parallel with the first memory column, wherein each memory column includes a differential threshold MOS transistor;
wherein one or more of the differential threshold transistors are transistors that each have a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage;
wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region, and wherein each insulating portion defines a threshold voltage between the gate and the first region or the second region associated with each insulating portion; and
a gate portion above the insulating layer;
wherein the first insulating portion or the second insulating portion is fabricated of varying length and width, and of different dimension than the opposed insulating portion, to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.
17. The sensing circuit of claim 16 further comprising one or more additional memory columns.
18. The sensing circuit of claim 16 wherein the first differential threshold NMOS transistor is a cascoding transistor.
19. The sensing circuit of claim 16 wherein one or more of the differential threshold transistor(s) is/are cascoding transistor(s).
20. The sensing circuit of claim 16 wherein one or more of the differential threshold MOS transistors are transistors having a channel region including a first junction region and a second junction region, wherein shape of the first insulating portion or shape or implantation of the first junction region are of varying dimension to provide a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage specified via dimension of one or both of the second insulating portion and/or the second junction region.
21. The sensing circuit of claim 16 wherein one or more of the differential threshold transistors includes a channel region comprising junction regions including a first junction region adjacent the first region and a second junction region adjacent the second region, the first junction region and the second junction region being opposed from each other; and
wherein one or both of shape or implantation of the first junction region or the second junction region are of varying dimension to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed junction region.
22. The sensing circuit of claim 16 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
a charge trapping region that yields a first threshold voltage associated with the first region or a second threshold voltage associated with the second region.
23. The sensing circuit of claim 16 wherein the first insulating portion is varied to provide for the differing first threshold voltage.
24. The sensing circuit of claim 16 wherein a width of the first insulating portion is varied to provide for the differing first threshold voltage.
25. The sensing circuit of claim 16 wherein the first insulating portion includes a region of oxide material removed from the insulating layer to effect a threshold voltage that differs from the second threshold voltage of the second insulating portion.
26. The sensing circuit of claim 16 wherein one or more of the differential threshold MOS transistors are transistors having a channel region including a first junction region and a second junction region, wherein shape of the first insulating portion or shape or implantation of the first junction region are of varying dimension to provide a gate-to-source threshold voltage that differs from a gate-to-drain threshold voltage specified via dimension of one or both of the second insulating portion and/or the second junction region.
27. The sensing circuit of claim 16 wherein one or more of the differential threshold transistors includes a channel region comprising junction regions including a first junction region adjacent the first region and a second junction region adjacent the second region, the first junction region and the second junction region being opposed from each other; and
wherein one or both of shape or implantation of the first junction region or the second junction region are of varying dimension to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed junction region.
28. The sensing circuit of claim 16 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
a charge trapping region that yields a first threshold voltage associated with the first region or a second threshold voltage associated with the second region.
29. The sensing circuit of claim 16 wherein one or more of the differential threshold transistors comprises:
a substrate of semiconductor material of a first conductivity type;
a first region and a second region in the substrate, wherein the first region and the second region are of a second conductivity type and spaced apart from each other defining a channel region therebetween;
an insulating layer disposed over the channel region of the substrate, wherein the insulating layer comprises opposed insulating portions including a first insulating portion adjacent the first region and a second insulating portion adjacent the second region, and wherein each insulating portion defines a threshold voltage between the gate and the first region or the second region associated with each insulating portion; and
a gate portion above the insulating layer;
wherein the first insulating portion or the second insulating portion is fabricated of varying length and width, and of different dimension than the opposed insulating portion, to provide a first threshold voltage that differs from a second threshold voltage associated with the opposed insulating portion.