Granted Patent B2

US 8,435,837 · App. 12/638,827 · Granted May 7, 2013

Abstract

Claims (17)

1. A method of packaging an integrated circuit die comprising:

a) placing a plurality of integrated circuit dies on a first substrate having a planar surface, each of said plurality of dies has a top surface and a bottom surface with the top surface having a plurality of bonding pads for electrical connection to said die; said plurality of dies positioned with said top surface in contact with said planar surface of said first substrate;

b) applying a conductive adhesive to the bottom surface of each of said dies;

c) placing a plurality of connected lead frames on said plurality of dies; each lead frame having a central recessed portion, and a plurality of conductive leads with each lead having a top side and a bottom side, said central recessed portion connected to said plurality of leads by a connection, with said central recessed portion having a top portion and a bottom portion with the bottom portion substantially co-planar with the bottom side of the plurality of leads, said central recessed portion of said lead frame placed on said conductive adhesive of said plurality of dies with said top portion of said recessed portion in contact with said conductive adhesive until the top side of each lead is in contact with said planar surface of said first substrate;

d) removing said first substrate;

e) placing the plurality of lead frames with said plurality of dies on a second substrate having a planar surface, with said bottom side of each lead and the bottom portion of the recessed portion on said planar surface of said second substrate;

f) depositing a conductive layer on said top surface of said die and said top side of said leads;

g) patterning the conductive layer to electrically connect certain of said bonding pads of one of said plurality of dies to certain of conductive leads associated with said one die; and

h) cutting each of said connection of each lead frame from adjacent lead frames and the leads from said recessed portion.

2. The method of claim 1 further comprising the step of filling the structure formed after step c) with an insulator to fill the space between each die and its adjacent leads of the associated lead frame.

3. The method of claim 2 further comprising the step of planarizing the structure formed after step (d) to remove any insulator on the bottom side of each lead and the bottom portion of the recessed portion.

4. The method of claim 2 wherein said depositing step deposits a conductive layer on said top surface of said die and said top side of said leads and over said insulator between each die and the adjacent leads of the associated lead frame.

5. The method of claim 4 wherein said conductive layer is patterned to form passive circuit elements connecting certain of said bonding pads of one of said plurality of dies to certain of conductive leads associated with said one die.

6. The method of claim 4 further comprising

attaching a conductive bump of a solder material to the bottom side of each lead.

7. The method of claim 6 further comprising

attaching a conductive bump of a solder material to the top side of each lead.

Assignments (15)