Flash memory array system including a top gate memory cell
View Patent ↗A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
1. A memory system comprising:
a plurality of memory cells arranged in sectors, the top gates of a first group of memory cells in a sector being coupled to a first line, source lines of a second group of memory cells in the sector being coupled to a second line, the top gates of a third group of memory cells in the sector being coupled to a third line, source lines of a fourth group of memory cells in the sector being coupled to a fourth line, the first group including memory cells in the second and fourth groups, the third group including memory cells in the second and fourth groups, but not in the first group.
2. The memory system of claim 1 wherein the memory cells are multilevel memory cells.
3. The memory system of claim 2 wherein the memory cells are tip erased memory cells.
4. The memory system of claim 2 wherein the memory cells are source side injection memory cells.
5. The memory system of claim 2 , wherein each memory cell further comprising:
a floating gate,
wherein said floating gate having a tip adjacent to said top gate for erasing said floating gate through said tip to said top gate.
6. The memory system of claim 2 further comprising:
a plurality of word lines coupled to at least one other individual line.
7. The memory system of claim 2 further comprising an enable transistor that controls a top gate line including one or both of the first line and/or the third line, wherein the enable transistor is configured to be turned off after a top gate reaches a bias level so that the top gate line floats and follows voltages on a word line.
8. The memory system of claim 2 wherein one or both of the first line and/or the third line are floating.
9. The memory system of claim 2 further comprising a first weak driver for driving a word line, and a second weak driver for driving one or both of the first line and/or the third line.
10. The memory system of claim 9 wherein one or both of the first line and/or the third line are floating.
11. The memory system of claim 2 further comprising a weak driver for driving one or both of the first line and/or the third line.
12. The memory system of claim 1 wherein the memory cells are tip erased memory cells.
13. The memory system of claim 1 wherein the memory cells are source side injection memory cells.
14. The memory system of claim 1 , wherein each memory cell further comprising:
a floating gate,
wherein said floating gate having a tip adjacent to said top gate for erasing said floating gate through said tip to said top gate.
15. The memory system of claim 1 further comprising:
a plurality of word lines coupled to at least one other individual line.
16. The memory system of claim 1 further comprising an enable transistor that controls a top gate line including one or both of the first line and/or the third line, wherein the enable transistor is configured to be turned off after a top gate reaches a bias level so that the top gate line floats and follows voltages on a word line.
17. The memory system of claim 1 wherein one or both of the first line and/or the third line are floating.
18. The memory system of claim 1 further comprising a first weak driver for driving a word line, and a second weak driver for driving one or both of the first line and/or the third line.
19. The memory system of claim 18 wherein one or both of the first line and/or the third line are floating.
20. The memory system of claim 1 further comprising a weak driver for driving one or both of the first line and/or the third line.