Method of manufacturing an array of bi-directional nonvolatile memory cells
View Patent ↗A method of making an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material, where the material has a first conductivity type with the substrate having a substantially planar surface, comprises forming a plurality of spaced apart substantially parallel trenches in a first direction in the planar surface. Each of the trenches has a sidewall and a bottom. A region of a second conductivity type is formed in the bottom of each trench. A floating gate is formed in each trench insulated and spaced apart from the sidewall of the trench. The floating gate has a first end near the bottom and a second end furthest away from the bottom. A layer of tunneling oxide is formed about the second end of each floating gate. A layer of word region is formed on the layer of tunneling oxide. The layer of word region extends in a second direction substantially perpendicular to the first direction. The layer of word region is cut into a plurality of strips in the second direction to form a plurality of spaced apart word lines. Each strip is spaced apart from one another and substantially parallel to one another, and cuts through the floating gate in each of the trenches. Electrical connections are made to each of the region of second conductivity type and each of the plurality of spaced apart word lines.
1. A method of forming an array of bi-directional non-volatile memory cells in a substrate of a substantially single crystalline semiconductive material having a first conductivity type, said substrate having a substantially planar surface, said method comprising:
forming a plurality of spaced apart substantially parallel trenches in a first direction in said planar surface; each trench having a sidewall and a bottom;
forming a region of a second conductivity type in said bottom of each trench;
forming a floating gate in each trench insulated and spaced apart from said sidewall of said trench; said floating gate having a first end near said bottom and a second end furthest away from said bottom;
forming a layer of tunneling oxide about said second end of each floating gate;
forming a layer of word region on said layer of tunneling oxide; said layer of word region extending in a second direction substantially perpendicular to said first direction;
cutting said layer of word region in a plurality of strips in said second direction to form a plurality of spaced apart word lines; each strip spaced apart from one another and substantially parallel to one another, and cutting through the floating gate in each trench; and
forming an electrical connection to each of said region of second conductivity type and each of said plurality of spaced apart word lines.
2. The method of claim 1 further comprising the steps of:
forming a plurality of spaced apart strips of protective material on said planar surface;
using said plurality of spaced apart strips of protective material as mask to form said plurality of spaced apart substantially parallel trenches.
3. The method of claim 2 wherein said protective material is silicon nitride.
4. The method of claim 1 wherein said step of forming a floating gate in each trench further comprises:
depositing a layer of insulating material along said sidewall and bottom of each trench; and
conformally depositing a layer of polysilicon on said layer of insulating material;
anisotropically etching said polysilicon to form said floating gate.
5. The method of claim 4 wherein each floating gate is insulated and spaced apart from said bottom of each trench.
6. The method of claim 1 wherein said forming a region step comprises ion implanting dopants of said second conductivity into the bottom of each trench.