Method of operating a split gate flash memory cell with coupling gate
View Patent ↗A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.
1. A method of erasing a memory cell that comprises a substrate of a first conductivity type, first and second regions spaced apart in the substrate of a second conductivity type which define a channel region in the substrate therebetween, a floating gate disposed over and insulated from a first portion of the channel region and the first region, a control gate having first and second portions, wherein the control gate first portion is disposed over and insulated from a second portion of the channel region and is disposed laterally adjacent to and insulated from the floating gate, wherein the control gate second portion is disposed over and insulated from the floating gate, and a coupling gate disposed over and insulated from the first region and laterally adjacent to and insulated from the floating gate, the method comprising:
applying a positive voltage to the control gate; and
applying a negative voltage to the coupling gate.
2. The method of claim 1 , further comprising:
applying a ground voltage to the first and second regions.
3. The method of claim 1 , wherein the positive voltage applied to the control gate is less than 10 volts.