Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor
View Patent ↗A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type;
a trench formed into a surface of the substrate;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region therebetween, wherein the second region is formed underneath the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate;
an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region and a portion of the first region;
an electrically conductive control gate having a first portion disposed in the trench; and
insulation material disposed between the floating gate and the control gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
2. The device of claim 1 , wherein the control gate has a second portion disposed over and insulated from the floating gate.
3. The device of claim 2 , wherein the control gate forms a notch at a connection between the control gate first portion and the control gate second portion.
4. The device of claim 3 , wherein the floating gate includes a sharp edge that extends toward the notch.
5. The device of claim 1 , wherein the channel region second portion extends from the channel region first portion to the first region, and wherein the floating gate is disposed over the entire second portion of the channel region.
6. The device of claim 2 , wherein the floating gate has a first end disposed over and insulated from the first region, and a second end disposed over and insulated from the channel region, and wherein the floating gate second end includes a sloping upper surface that terminates in a sharp edge that extends toward the control gate.
7. The device of claim 2 , further comprising:
the insulating material is formed along sidewalls of the trench and extends between the control gate and the floating gate.
8. The device of claim 7 , wherein the insulating material is a layer of the insulating material that includes:
a first portion formed along sidewalls of the trench and between the control gate and the channel region first portion; and
a second portion formed under the control gate and over the floating gate.
9. The device of claim 1 , wherein channel region first portion extends in a direction directly toward the floating gate.
10. The device of claim 1 , wherein the trench has a side wall with an indentation formed therein, and wherein the control gate first portion includes a protruding portion corresponding to the indentation that extends over and is insulated from a portion of the floating gate.
11. The device of claim 1 , wherein:
the trench has a side wall with an indentation formed therein,
the control gate first portion includes a protruding portion corresponding to the indentation that extends over and is insulated from a first part of the channel region second portion, and
the floating gate is disposed over and insulated from a second part of the channel region second portion.
12. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
a plurality of trenches formed into a surface of the substrate which are substantially parallel to one another and extend across the isolation and active regions in a second direction that is substantially perpendicular to the first direction;
each of the active regions including a plurality of memory cells extending in the first direction, each of the memory cells comprising:
first and second spaced-apart regions formed in the substrate having a second conductivity type, with a channel region formed in the substrate therebetween, wherein the second region is formed underneath one of the trenches, and wherein the channel region has a first portion extending substantially along a sidewall of the one trench and a second portion extending substantially along the surface of the substrate, and
an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region and a portion of the first region; and
a plurality of electrically conductive control gates each extending along one of the active regions, wherein the control gates each have first portions disposed in the trenches;
wherein for each of the memory cells, insulation material is disposed between the floating gate and the control gate that has a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
13. The array of claim 12 , wherein the control gates each have second portions disposed over and insulated from the floating gates.
14. The array of claim 13 , wherein the control gates form notches at points where the control gate first and the second portions meet.
15. The array of claim 14 , wherein the floating gates include sharp edges that extend toward the notches.
16. The array of claim 12 , further comprising:
a layer of isolation material extending along each of the isolation regions and filling portions of the trenches that are in the isolation regions.
17. The array of claim 16 , wherein the isolation material layer in each of the isolation regions is disposed between a pair of the control gates in adjacent active regions.
18. The array of claim 12 , wherein for each of the memory cells, the channel region second portion extends from the channel region first portion to the first region, and wherein the floating gate is disposed over the entire second portion of the channel region.
19. The array of claim 13 , wherein for each of the memory cells, the floating gate has a first end disposed over and insulated from the first region, and a second end disposed over and insulated from the channel region, and wherein the floating gate second end includes a sloping upper surface that terminates in a sharp edge that extends toward the control gate.
20. The array of claim 13 , wherein for each of the memory cells, the insulating material is formed along sidewalls of the trench and extends between the control gate and the floating gate.
21. The array of claim 20 , wherein the insulating material for each memory cell is a layer of the insulating material that includes:
a first portion formed along sidewalls of the trench and between the control gate and the channel region first portion; and
a second portion formed under the control gate and over the floating gate.
22. The array of claim 12 , further comprising a plurality of conductive contacts each electrically connected to one of the first regions.
23. The array of claim 12 , further comprising a plurality of conductive contacts each electrically connected to one of the second regions.
24. The array of claim 12 , wherein each of the channel region first portions extend in a direction directly toward one of the floating gates.
25. The array of claim 12 , wherein the memory cells are formed as pairs of memory cells, and wherein each of the memory cell pairs share a single second region therebetween.
26. The array of claim 12 , wherein for each of the memory cells, the trench has a side wall with an indentation formed therein, and the control gate first portion includes a protruding portion corresponding to the indentation that extends over and is insulated from a portion of the floating gate.
27. The array of claim 12 wherein for each of the memory cells:
the trench has a side wall with an indentation formed therein,
the control gate first portion includes a protruding portion corresponding to the indentation that extends over and is insulated from a first part of the channel region second portion, and
the floating gate is disposed over and insulated from a second part of the channel region second portion.
28. The array of claim 12 wherein the second regions are integrally formed together in one of a plurality of conductive lines buried in the substrate, and wherein each of the conductive lines extends in the second direction and includes a raised portion that extends up to the substrate surface.
29. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type;
a trench formed into a surface of the substrate;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a non-linear channel region therebetween, wherein the second region is formed underneath the trench, and wherein the channel region includes a first portion extending generally along a sidewall of the wrench and a second portion extending generally along the surface of the substrate;
an electrically conductive control gate having a first portion disposed in the trench;
a floating gate disposed over and insulated from the substrate surface, wherein the floating gate has a first end disposed over and insulated from the first region, and a second end disposed over and insulated from the channel region, and wherein the floating gate second end includes a sloping upper surface that terminates in a sharp edge that extends toward the control gate; and
insulation material disposed between the floating gate and the control gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
30. The device of claim 29 , wherein at least a portion of the non-linearity of the channel region is defined within a plane that is substantially perpendicular to the substrate surface.
31. The device of claim 29 , wherein the channel region first portion extends in a direction from the second region directly toward the floating gate.
32. The device of claim 31 , wherein the direction is substantially perpendicular to the substrate surface.
33. The device of claim 31 , wherein the channel region second portion extends in a direction from the channel region first portion to the first region.
34. The device of claim 29 , wherein:
the channel region first portion extends in a direction from the second region toward the surface of the substrate;
the channel region second portion extends in a direction from the channel region first portion to the first region; and
the floating gate is disposed over and insulated from only a portion of the channel region second portion.
35. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material of a first conductivity type;
an electrically conductive control gate having a first portion formed in the substrate;
first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a non-linear channel region therebetween, wherein the second region is formed underneath and is insulated from the control gate first portion, and the channel region includes a first portion that extends substantially along the control gate first portion and a second portion that extends substantially along a surface of the substrate;
an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region and a portion of the first region; and
insulation material disposed between the floating gate and the control gate and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
36. The device of claim 35 , wherein the control gate has a second portion disposed over and insulated from the floating gate.
37. The device of claim 35 , wherein the channel region second portion extends from the channel region first portion to the first region, and wherein the floating gate is disposed over the entire second portion of the channel region.
38. The device of claim 37 , wherein channel region first portion extends in a direction directly toward the floating gate.
39. The device of claim 35 , wherein the floating gate is disposed over only a portion of the channel region second portion.
40. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material of a first conductivity type and having a surface;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the active regions including a plurality of memory cells, wherein each of the memory cells, includes an electrically conductive floating gate disposed over and insulated from the substrate surface;
a plurality of first regions formed in the substrate and having a second conductivity type, each of the first regions extends across the active regions in a second direction perpendicular to the first direction and is disposed at least partially underneath one of the floating gates in each of the active regions;
a plurality of second regions formed in the substrate and having the second conductivity type, each of the second regions extends across the active regions in the second direction and is disposed between a pair of the first regions, wherein the second regions are buried underneath the substrate surface; and
a plurality of electrically conductive control gates each extending along one of the active regions in the first direction, wherein the control gates are insulated from the floating gates by insulation material having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.
41. The array of claim 40 , wherein each of the control gates includes a plurality of first portions that are each disposed in the substrate and over one of the second regions.
42. The array of claim 41 , wherein for each of the active regions, the control gate therein has a second portion that is disposed over and insulated from the floating gates.
43. The array of claim 40 , further comprising:
a plurality of channel regions in the substrate each extending between one of the first regions and one of the second regions.
44. The array of claim 43 , wherein each of the channel regions has a first portion extending from one of the second regions toward the substrate surface, and a second portion extending substantially along the substrate surface.
45. The array of claim 40 wherein the second regions are integrally formed together in one of a plurality of conductive lines buried in the substrate, and wherein each of the conductive lines extends in the second direction and includes a raised portion that extends up to the substrate surface.