Digital multilevel non-volatile memory system
View Patent ↗A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.
1. A method of determining data stored in a multilevel memory cell, the method comprising:
setting the memory cell in a current sensing mode;
setting a bit of the data;
dividing a reference current range into two sub-ranges to determine a divided reference value;
comparing a voltage sensed from the data cell to the divided reference value;
setting a corresponding bit based on said comparison; and
repeating said setting a bit, dividing, comparing and setting a corresponding bit for each bit of the data.
2. The method of claim 1 wherein the two sub-ranges are equal.
3. The method of claim 1 wherein the current sensing mode includes an autozero mode.
4. The method of claim 1 wherein the multilevel memory cell is a nonvolatile memory cell.
5. A method for reading a multilevel memory cell, the method comprising:
setting the memory cell in a current sensing mode;
comparing a current of the memory cell to a predetermined number of a plurality of reference values in a current range;
determining a first bit based on a comparison to a reference current of said predetermined number of reference values that is near the middle of the range and determining a second less significant bit by comparing to other of predetermined number of reference levels;
comparing the value of the data cell to reference levels in a subrange corresponding to the selected most significant bit and differing from said predetermined number of reference values; and
determining said bits based on said comparison.
6. The method of claim 5 further comprising:
ignoring some of said comparing to ones of said predetermined number of plurality of reference values based on said determined first bit.
7. The method of claim 5 wherein the current sensing mode includes an autozero mode.
8. The method of claim 5 wherein the memory cell is a nonvolatile memory cell.
9. A data storage system comprising:
a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, each bitline coupling a column of said memory cells, and including a plurality of source lines, each source line coupling a portion of memory cells in a row of memory cells;
a first control circuit to apply a reference voltage on a selected bitline;
a second control circuit to apply a predetermined read bias current on a selected source line and
a read circuit to sense voltage on said selected source line and provide an output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected source line.
10. The data storage system of claim 9 wherein the memory cells are nonvolatile memory cells.
11. The data storage system of claim 9 wherein the memory cells are multilevel nonvolatile memory cells.
12. The data storage system of claim 9 wherein the memory cells are multilevel memory cells.
13. The data storage system of claim 9 comprising an autozero circuit to couple said selected source line to an output signal of said read circuit prior to said sensed readout voltage on the selected source line.
14. A data storage system comprising:
a plurality of memory arrays, each memory array including a plurality of memory cells arranged in rows and columns, including a plurality of bitlines, and including a plurality of source lines, each bitline coupling the column of said memory cells, each source line coupling a portion of memory cells in a row of memory cells;
a first control circuit to apply a reference voltage on a selected bitline;
a second control circuit to apply a predetermined bias voltage on a selected source line; and
a read circuit to sense voltage on said selected source line and provided output signal indicative of the content of selected memory cells in response to a sensed readout voltage on the selected source line.