Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates
View Patent ↗An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
1. An array of non-volatile memory cells comprising:
a semiconductor substrate of a first conductivity type having a top surface;
a plurality of spaced apart first regions of a second conductivity type in said substrate along the top surface, each first region extending in a row direction;
a plurality of spaced apart second regions of the second conductivity type, in said substrate along the top surface, each second region spaced apart from an associated first region in a column direction, perpendicular to the row direction;
a plurality of spaced apart channel regions, with each channel region between a second region and its associated first region in the column direction; each of said channel regions having a first portion and a second portion;
a plurality of spaced apart word line gates extending in the row direction, with each word line gate positioned over and insulated from the first portion of a plurality of channel regions, with each first portion of channel region immediately adjacent to the second region;
a plurality of spaced apart floating gates, each floating gate positioned over the second portion of the channel region and insulated therefrom;
a plurality of spaced apart coupling gates extending in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates;
a plurality of spaced apart metal strapping lines extending in the row direction, with each metal strapping line associated with and overlying a coupling gate, with a metal strapping line in a first row electrically connected to the associated underlying coupling gate in a plurality of first locations, and a metal strapping line in a row immediately adjacent to the first row electrically connected to the associated underlying coupling gate in a plurality of second locations, with said first locations and said second locations not in the same column; and
a plurality of spaced apart erase gates, extending in said row direction, with each erase gate positioned over a first region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate.
2. The array of claim 1 wherein each erase gate overhangs a portion of an adjacent floating gate.
3. The array of claim 1 wherein said first locations are spaced apart from one another by 256 columns, and said second locations are spaced apart from one another by 256 columns.
4. The array of claim 3 wherein each of said first locations and said second locations is offset from one another by 128 columns.
5. An array of non-volatile memory cells comprising:
a semiconductor substrate of a first conductivity type having a top surface;
a plurality of spaced apart first regions of a second conductivity type in said substrate along the top surface, each first region extending in a row direction;
a plurality of spaced apart second regions of the second conductivity type, in said substrate along the top surface, each second region spaced apart from an associated first region in a column direction, perpendicular to the row direction;
a plurality of spaced apart channel regions, with each channel region between a second region and its associated first region in the column direction; each of said channel regions having a first portion and a second portion;
a plurality of spaced apart word line gates extending in the row direction, with each word line gate positioned over and insulated from the first portion of a plurality of channel regions, with each first portion of channel region immediately adjacent to the second region;
a plurality of spaced apart floating gates, each floating gate positioned over the second portion of the channel region and insulated therefrom;
a plurality of spaced apart coupling gates extending in the row direction, with each coupling gate extending over and insulated from a plurality of floating gates;
a plurality of spaced apart metal strapping lines extending in the row direction, with each metal strapping line associated with and overlying a coupling gate, with each metal strapping lines in a first alternating rows electrically connected to the associated underlying coupling gate in a plurality of first locations, and each metal strapping lines in a second alternating rows immediately adjacent to the first alternating rows electrically connected to the associated underlying coupling gate in a plurality of second locations, with said first locations and said second locations not in the same column; and
a plurality of spaced apart erase gates, extending in said row direction, with each erase gate positioned over a first region and insulated therefrom, and adjacent to and insulated from a floating gate and coupling gate.
6. The array of claim 5 wherein each erase gate overhangs a portion of an adjacent floating gate.
7. The array of claim 5 wherein said first locations are spaced apart from one another by 256 columns, and said second locations are spaced apart from one another by 256 columns.
8. The array of claim 7 wherein each of said first locations and said second locations is offset from one another by 128 columns.