Power management for a memory device
View Patent ↗An improved method and apparatus for performing power management in a memory device is disclosed.
1. A power management circuit for use in a memory device, comprising:
a system device clock for generating a clock signal;
a timing circuit comprising a plurality of timing stages, wherein each of the plurality of timing stages generates a time period output indicating the completion of a time period, each of the time periods for the plurality of timing stages being different from one another;
a counter for generating a plurality of count bits indicating a number of clock pulses counted in the clock signal;
a plurality of logic gates, each of the logic gates receiving a time period output from one of the plurality of timing stages and one of the plurality of count bits from the counter and generating a gate output;
combinatorial logic for receiving a gate output from each of the plurality of logic gates and outputting a power signal indicating a power level, wherein the power level is proportional to the frequency of the clock signal;
a bias voltage modulator for providing a bias voltage to a sense amplifier in response to the power signal.
2. The power management circuit of claim 1 , wherein the bias voltage modulator alters the bias voltage of the sense amplifier in response to changes in the power signal.
3. A power management method for a memory device, comprising:
generating, by a system device clock, a clock signal;
generating, by a plurality of timing stages, a plurality of time period outputs, each time period output indicating the completion of a different time period;
generating, by a counter, a plurality of count bits indicating the number of clock pulses within the clock signal;
generating, by a plurality of logic gates, a plurality of gate outputs, wherein each of the plurality of logic gates receives a time period output and a count bit and generates a gate output;
outputting, by combinatorial logic, a power signal indicating a power level in response to the plurality of gate outputs, wherein the power level is proportional to the frequency of the clock signal; and
providing, by a bias voltage modulator, a bias voltage to a sense amplifier in response to the power signal.
4. The method of claim 3 , wherein the bias voltage modulator alters the bias voltage of the sense amplifier in response to changes in the power signal.