Non-volatile memory cells with enhanced channel region effective width, and method of making same
View Patent ↗A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.
1. An array of memory devices, comprising:
a substrate of semiconductor material having a first conductivity type and a top surface;
spaced apart isolation regions formed in the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;
each of the isolation regions includes a trench formed into and extending below the top surface of the substrate and an insulation material formed in the trench, wherein at least portions of a top surface of the insulation material are recessed below the top surface of the substrate;
each of the active regions including a column of memory cells, wherein each of the memory cells comprises:
spaced apart first and second regions formed along the top surface of the substrate and having a second conductivity type different than the first conductivity type, wherein a channel region of the substrate is disposed between the first and second regions,
a floating gate disposed over and insulated from a first portion of the channel region, and
a select gate disposed over and insulated from a second portion of the channel region;
wherein the select gates are formed as continuous word lines each extending in a second direction perpendicular to the first direction and each forming the select gate for one of the memory cells in each of the columns of memory cells, and wherein portions of each of the word lines extend down into the trenches and over the insulation material in the isolation regions such that for each memory cell:
a first portion of the word line is disposed over and insulated from the top surface of the substrate,
a second portion of the word line is disposed laterally adjacent to and insulated from a first sidewall of one of the trenches extending down from the top surface of the substrate,
a third portion of the word line is disposed laterally adjacent to and insulated from a second sidewall of another one of the trenches extending down from the top surface of the substrate,
such that the top surface of the substrate and the first and second sidewalls form the channel region; and
wherein each of the floating gates is conductive material disposed over and insulated from the top surface of the substrate without any portion thereof extending into any of the trenches.
2. The array of memory devices of claim 1 , wherein each of the memory cells further comprises:
a control gate disposed over and insulated from the floating gate; and
an erase gate disposed over and insulated from the first region.
3. The array of memory devices of claim 2 , wherein for each of the memory cells, a portion of the floating gate is disposed over and insulated from the first region.
4. A method of forming an array of memory devices, comprising:
providing a substrate of semiconductor material having a first conductivity type and a top surface;
forming spaced apart isolation regions in the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein each of the isolation regions are formed by:
forming a trench into and extending below the top surface of the substrate, and
forming insulation material in the trench, wherein at least portions of a top surface of the insulation material are recessed below the top surface of the substrate;
forming a column of memory cells in each of the active regions, wherein forming each memory cell comprises:
forming spaced apart first and second regions along the top surface of the substrate having a second conductivity type different than the first conductivity type, wherein a channel region of the substrate is disposed between the first and second regions,
forming a floating gate over and insulated from a first portion of the channel region, and
forming a select gate over and insulated from a second portion of the channel region;
wherein the select gates are formed as continuous word lines each extending in a second direction perpendicular to the first direction and each forming the select gate for one of the memory cells in each of the columns of memory cells, and wherein portions of each of the word lines extend down into the trenches and over the insulation material in the isolation regions such that for each memory cell:
a first portion of the word line is disposed over and insulated from the top surface of the substrate,
a second portion of the word line is disposed laterally adjacent to and insulated from a first sidewall of one of the trenches extending down from the top surface of the substrate,
a third portion of the word line is disposed laterally adjacent to and insulated from a second sidewall of another one of the trenches extending down from the top surface of the substrate,
such that the top surface of the substrate and the first and second sidewalls form the channel region; and
wherein each of the floating gates is conductive material disposed over and insulated from the top surface of the substrate without any portion thereof extending into any of the trenches.
5. The method of claim 4 , wherein forming each of the memory cells further comprises:
forming a control gate over and insulated from the floating gate; and
forming an erase gate over and insulated from the first region.
6. The method of claim 5 , wherein for each of the memory cells, a portion of the floating gate is disposed over and insulated from the first region.
7. The method of claim 4 , wherein the forming of each of the isolation regions comprises:
forming the trench into the top surface of the substrate;
forming the insulation material in the trench; and
removing top portions of the insulation material in the trench such that the at least portions of the top surface of the insulation material is recessed below the top surface of the substrate.