Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby
View Patent ↗A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
1. An electrically programmable and erasable memory device comprising:
a substrate of semiconductor material having a first conductivity type;
first and second regions formed in the substrate and having a second conductivity type, wherein the first and second regions are spaced apart from each other with a channel region formed in the substrate therebetween, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region;
an electrically conductive floating gate having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from the channel region first portion for controlling a conductivity thereof, wherein the floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge;
a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portion, and a second portion that extends up and over and is insulated from the floating gate first portion; and
an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity thereof.
2. The device of claim 1 , wherein the control gate comprises a first portion that is laterally adjacent to and insulated from the floating gate second portion, and a second portion that extends up and over and is insulated from the floating gate second portion.
3. The device of claim 1 , wherein the floating gate second portion includes a generally planar horizontally extending upper surface portion disposed under the control gate.
4. The device of claim 1 , wherein the acute edge directly faces and is insulated from the block of conductive material.
5. The device of claim 1 , wherein the block of conductive material comprises:
a first portion that is a spacer of conductive material having a first portion that is laterally adjacent to and insulated from the floating gate first portion and a second portion that extends up and over and is insulated from the floating gate first portion; and
a second portion of conductive material that is disposed over and in electrical contact with the first region, and is disposed adjacent to and in electrical contact with the spacer.
6. The device of claim 5 , wherein the acute edge directly faces and is insulated from the spacer of conductive material.
7. The device of claim 1 , wherein the block of conductive material is insulated from the floating gate by insulation material having a thickness that permits Fowler-Nordheim tunneling.
8. An array of electrically programmable and erasable memory devices comprising:
a substrate of semiconductor material having a first conductivity type;
spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and
each of the active regions including a plurality of pairs of memory cells, wherein each of the memory cell pairs comprises:
a first region formed in the substrate,
a pair of second regions formed in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion adjacent the first region and a second portion adjacent one of the second regions,
a pair of electrically conductive floating gates each having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from one of the channel region first portions for controlling a conductivity thereof, wherein each of the floating gate first portions includes a sloped upper surface and a side surface that meet at an acute edge,
a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portions, and a second portion that extends up and over and is insulated from the floating gate first portions, and
a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity thereof.
9. The array of claim 8 , wherein each of the control gates comprises a first portion that is laterally adjacent to and insulated from one of the floating gate second portions, and a second portion that extends up and over and is insulated from one of the floating gate second portions.
10. The array of claim 8 , wherein each of the floating gate second portions includes a generally planar horizontally extending upper surface portion disposed under one of the control gates.
11. The array of claim 8 , wherein each of the acute edges directly faces and is insulated from the block of conductive material.
12. The array of claim 8 , wherein each of the blocks of conductive material comprises:
a first portion that is a pair of spacers of conductive material each having a first portion that is laterally adjacent to and insulated from one of the floating gate first portions and a second portion that extends up and over and is insulated from one of the floating gate first portions; and
a second portion of conductive material that is disposed over and in electrical contact with the first region, and is disposed adjacent to and in electrical contact with the spacers.
13. The array of claim 12 , wherein each of the acute edges directly faces and is insulated from one of the spacers of the conductive material.
14. The array of claim 8 , wherein the block of conductive material is insulated from each of the floating gates by insulation material having a thickness that permits Fowler-Nordheim tunneling.
15. The array of claim 8 , further comprising:
a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
16. The array of claim 8 , further comprising:
a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the conductive blocks from each of the active regions.
17. A method of forming a semiconductor memory cell, comprising:
forming first and second regions of a second conductivity type in a substrate of a first conductivity type, wherein the first and second regions are spaced apart from each other with a channel region in the substrate therebetween, and wherein the channel region includes a first portion adjacent the first region and a second portion adjacent the second region;
forming an electrically conductive floating gate having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from the channel region first portion for controlling a conductivity thereof, wherein the floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge;
forming a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portion, and a second portion that extends up and over and is insulated from the floating gate first portion; and
forming an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity thereof.
18. The method of claim 17 , wherein the control gate comprises a first portion that is laterally adjacent to and insulated from the floating gate second portion, and a second portion that extends up and over and is insulated from the floating gate second portion.
19. The method of claim 17 , wherein the floating gate second portion includes a generally planar horizontally extending upper surface portion disposed under the control gate.
20. The method of claim 17 , wherein the acute edge directly faces and is insulated from the block of conductive material.
21. The method of claim 17 , wherein the formation of the block of conductive material comprises:
forming a spacer of conductive material having a first portion that is laterally adjacent to and insulated from the floating gate first portion and a second portion that extends up and over and is insulated from the floating gate first portion; and
forming conductive material that is disposed over and in electrical contact with the first region, and is disposed adjacent to and in electrical contact with the spacer.
22. The method of claim 21 , wherein the acute edge directly faces and is insulated from the spacer of the conductive material.
23. The method of claim 17 , wherein the formation of the block of conductive material comprises:
forming a layer of insulation material along the sloped upper surface and the side surface that has a thickness that permits Fowler-Nordheim tunneling.
24. The method of claim 17 , wherein the formation of the floating gate comprises:
forming a layer of conductive material;
performing a slope etch on the layer of conductive material to form the sloped upper surface;
removing a portion of the conductive material layer adjacent the sloped upper surface to form the side surface that meets the sloped upper surface at the acute edge.
25. A method of forming an array of electrically programmable and erasable memory devices comprising:
forming spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, wherein the substrate has a first conductivity type; and
forming pairs of memory cells in each of the active regions, wherein the formation of each of the memory cell pairs comprises:
forming a first region in the substrate,
forming a pair of second regions in the substrate, with a pair of channel regions each formed in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion adjacent the first region and a second portion adjacent one of the second regions;
forming a pair of electrically conductive floating gates each having a first portion disposed over and insulated from the first region and a second portion disposed over and insulated from one of the channel region first portions for controlling a conductivity thereof, wherein each of the floating gate first portions includes a sloped upper surface and a side surface that meet at an acute edge;
forming a block of conductive material disposed over and in electrical contact with the first region, wherein the block of conductive material comprises a first portion that is laterally adjacent to and insulated from the floating gate first portions, and a second portion that extends up and over and is insulated from the floating gate first portions; and
forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity thereof.
26. The method of claim 25 , wherein each of the control gates comprises a first portion that is laterally adjacent to and insulated from one of the floating gate second portions, and a second portion that extends up and over and is insulated from one of the floating gate second portions.
27. The method of claim 25 , wherein each of the floating gate second portions includes a generally planar horizontally extending upper surface portion disposed under one of the control gates.
28. The method of claim 25 , wherein each of the acute edges directly faces and is insulated from the block of conductive material.
29. The method of claim 25 , wherein the formation of each of the blocks of conductive material comprises:
forming spacers of conductive material each having a first portion that is laterally adjacent to and insulated from one of the floating gate first portions and a second portion that extends up and over and is insulated from one of the floating gate first portions; and
forming conductive material that is disposed over and in electrical contact with the first region, and is disposed adjacent to and in electrical contact with the spacers.
30. The method of claim 29 , wherein each of the acute edges directly faces and is insulated from one of the spacers of the conductive material.
31. The method of claim 25 , wherein the formation of each of the blocks of conductive material comprises:
forming a layer of insulation material along the sloped upper surfaces and the side surfaces of the floating gates having a thickness that permits Fowler-Nordheim tunneling.
32. The method of claim 25 , wherein the formation of each of the floating gates comprises:
forming a layer of conductive material;
performing a slope etch on the layer of conductive material to form the sloped upper surface;
removing a portion of the conductive material layer adjacent the sloped upper surface to form the side surface that meets the sloped upper surface at the acute edge.
33. The method of claim 25 , further comprising:
forming a plurality of conductive control lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the control gates from each of the active regions.
34. The method of claim 25 , further comprising:
forming a plurality of conductive source lines of conductive material each extending across the active and isolation regions in a second direction perpendicular to the first direction and each electrically connecting together one of the conductive blocks from each of the active regions.